xref: /openbmc/linux/include/linux/mfd/abx500.h (revision 3d5e2cab)
1812f9e9dSLinus Walleij /*
2812f9e9dSLinus Walleij  * Copyright (C) 2007-2009 ST-Ericsson AB
3812f9e9dSLinus Walleij  * License terms: GNU General Public License (GPL) version 2
4812f9e9dSLinus Walleij  * AB3100 core access functions
5812f9e9dSLinus Walleij  * Author: Linus Walleij <linus.walleij@stericsson.com>
6fa661258SMattias Wallin  *
7fa661258SMattias Wallin  * ABX500 core access functions.
8fa661258SMattias Wallin  * The abx500 interface is used for the Analog Baseband chip
947c16975SMattias Wallin  * ab3100, ab3550, ab5500, and ab8500.
10fa661258SMattias Wallin  *
11fa661258SMattias Wallin  * Author: Mattias Wallin <mattias.wallin@stericsson.com>
12fa661258SMattias Wallin  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
13fa661258SMattias Wallin  * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
14fa661258SMattias Wallin  * Author: Rickard Andersson <rickard.andersson@stericsson.com>
15812f9e9dSLinus Walleij  */
16812f9e9dSLinus Walleij 
17812f9e9dSLinus Walleij #include <linux/device.h>
18812f9e9dSLinus Walleij #include <linux/regulator/machine.h>
19812f9e9dSLinus Walleij 
20fa661258SMattias Wallin #ifndef MFD_ABX500_H
21fa661258SMattias Wallin #define MFD_ABX500_H
22812f9e9dSLinus Walleij 
23fa661258SMattias Wallin #define AB3100_P1A	0xc0
24fa661258SMattias Wallin #define AB3100_P1B	0xc1
25fa661258SMattias Wallin #define AB3100_P1C	0xc2
26fa661258SMattias Wallin #define AB3100_P1D	0xc3
27fa661258SMattias Wallin #define AB3100_P1E	0xc4
28fa661258SMattias Wallin #define AB3100_P1F	0xc5
29fa661258SMattias Wallin #define AB3100_P1G	0xc6
30fa661258SMattias Wallin #define AB3100_R2A	0xc7
31fa661258SMattias Wallin #define AB3100_R2B	0xc8
32fa661258SMattias Wallin #define AB3550_P1A	0x10
33fa661258SMattias Wallin #define AB5500_1_0	0x20
343d5e2cabSMattias Wallin #define AB5500_1_1	0x21
353d5e2cabSMattias Wallin #define AB5500_2_0	0x24
36812f9e9dSLinus Walleij 
37863dde5bSLinus Walleij /* AB8500 CIDs*/
38863dde5bSLinus Walleij #define AB8500_CUTEARLY	0x00
39863dde5bSLinus Walleij #define AB8500_CUT1P0	0x10
40863dde5bSLinus Walleij #define AB8500_CUT1P1	0x11
41863dde5bSLinus Walleij #define AB8500_CUT2P0	0x20
42863dde5bSLinus Walleij #define AB8500_CUT3P0	0x30
43863dde5bSLinus Walleij 
44812f9e9dSLinus Walleij /*
45812f9e9dSLinus Walleij  * AB3100, EVENTA1, A2 and A3 event register flags
46812f9e9dSLinus Walleij  * these are catenated into a single 32-bit flag in the code
47812f9e9dSLinus Walleij  * for event notification broadcasts.
48812f9e9dSLinus Walleij  */
49812f9e9dSLinus Walleij #define AB3100_EVENTA1_ONSWA				(0x01<<16)
50812f9e9dSLinus Walleij #define AB3100_EVENTA1_ONSWB				(0x02<<16)
51812f9e9dSLinus Walleij #define AB3100_EVENTA1_ONSWC				(0x04<<16)
52812f9e9dSLinus Walleij #define AB3100_EVENTA1_DCIO				(0x08<<16)
53812f9e9dSLinus Walleij #define AB3100_EVENTA1_OVER_TEMP			(0x10<<16)
54812f9e9dSLinus Walleij #define AB3100_EVENTA1_SIM_OFF				(0x20<<16)
55812f9e9dSLinus Walleij #define AB3100_EVENTA1_VBUS				(0x40<<16)
56812f9e9dSLinus Walleij #define AB3100_EVENTA1_VSET_USB				(0x80<<16)
57812f9e9dSLinus Walleij 
58812f9e9dSLinus Walleij #define AB3100_EVENTA2_READY_TX				(0x01<<8)
59812f9e9dSLinus Walleij #define AB3100_EVENTA2_READY_RX				(0x02<<8)
60812f9e9dSLinus Walleij #define AB3100_EVENTA2_OVERRUN_ERROR			(0x04<<8)
61812f9e9dSLinus Walleij #define AB3100_EVENTA2_FRAMING_ERROR			(0x08<<8)
62812f9e9dSLinus Walleij #define AB3100_EVENTA2_CHARG_OVERCURRENT		(0x10<<8)
63812f9e9dSLinus Walleij #define AB3100_EVENTA2_MIDR				(0x20<<8)
64812f9e9dSLinus Walleij #define AB3100_EVENTA2_BATTERY_REM			(0x40<<8)
65812f9e9dSLinus Walleij #define AB3100_EVENTA2_ALARM				(0x80<<8)
66812f9e9dSLinus Walleij 
67812f9e9dSLinus Walleij #define AB3100_EVENTA3_ADC_TRIG5			(0x01)
68812f9e9dSLinus Walleij #define AB3100_EVENTA3_ADC_TRIG4			(0x02)
69812f9e9dSLinus Walleij #define AB3100_EVENTA3_ADC_TRIG3			(0x04)
70812f9e9dSLinus Walleij #define AB3100_EVENTA3_ADC_TRIG2			(0x08)
71812f9e9dSLinus Walleij #define AB3100_EVENTA3_ADC_TRIGVBAT			(0x10)
72812f9e9dSLinus Walleij #define AB3100_EVENTA3_ADC_TRIGVTX			(0x20)
73812f9e9dSLinus Walleij #define AB3100_EVENTA3_ADC_TRIG1			(0x40)
74812f9e9dSLinus Walleij #define AB3100_EVENTA3_ADC_TRIG0			(0x80)
75812f9e9dSLinus Walleij 
76812f9e9dSLinus Walleij /* AB3100, STR register flags */
77812f9e9dSLinus Walleij #define AB3100_STR_ONSWA				(0x01)
78812f9e9dSLinus Walleij #define AB3100_STR_ONSWB				(0x02)
79812f9e9dSLinus Walleij #define AB3100_STR_ONSWC				(0x04)
80812f9e9dSLinus Walleij #define AB3100_STR_DCIO					(0x08)
81812f9e9dSLinus Walleij #define AB3100_STR_BOOT_MODE				(0x10)
82812f9e9dSLinus Walleij #define AB3100_STR_SIM_OFF				(0x20)
83812f9e9dSLinus Walleij #define AB3100_STR_BATT_REMOVAL				(0x40)
84812f9e9dSLinus Walleij #define AB3100_STR_VBUS					(0x80)
85812f9e9dSLinus Walleij 
86812f9e9dSLinus Walleij /*
87812f9e9dSLinus Walleij  * AB3100 contains 8 regulators, one external regulator controller
88812f9e9dSLinus Walleij  * and a buck converter, further the LDO E and buck converter can
89812f9e9dSLinus Walleij  * have separate settings if they are in sleep mode, this is
90812f9e9dSLinus Walleij  * modeled as a separate regulator.
91812f9e9dSLinus Walleij  */
92812f9e9dSLinus Walleij #define AB3100_NUM_REGULATORS				10
93812f9e9dSLinus Walleij 
94812f9e9dSLinus Walleij /**
95812f9e9dSLinus Walleij  * struct ab3100
96812f9e9dSLinus Walleij  * @access_mutex: lock out concurrent accesses to the AB3100 registers
97812f9e9dSLinus Walleij  * @dev: pointer to the containing device
98812f9e9dSLinus Walleij  * @i2c_client: I2C client for this chip
99812f9e9dSLinus Walleij  * @testreg_client: secondary client for test registers
100812f9e9dSLinus Walleij  * @chip_name: name of this chip variant
101812f9e9dSLinus Walleij  * @chip_id: 8 bit chip ID for this chip variant
102812f9e9dSLinus Walleij  * @event_subscribers: event subscribers are listed here
103812f9e9dSLinus Walleij  * @startup_events: a copy of the first reading of the event registers
104812f9e9dSLinus Walleij  * @startup_events_read: whether the first events have been read
105812f9e9dSLinus Walleij  *
106812f9e9dSLinus Walleij  * This struct is PRIVATE and devices using it should NOT
107812f9e9dSLinus Walleij  * access ANY fields. It is used as a token for calling the
108812f9e9dSLinus Walleij  * AB3100 functions.
109812f9e9dSLinus Walleij  */
110812f9e9dSLinus Walleij struct ab3100 {
111812f9e9dSLinus Walleij 	struct mutex access_mutex;
112812f9e9dSLinus Walleij 	struct device *dev;
113812f9e9dSLinus Walleij 	struct i2c_client *i2c_client;
114812f9e9dSLinus Walleij 	struct i2c_client *testreg_client;
115812f9e9dSLinus Walleij 	char chip_name[32];
116812f9e9dSLinus Walleij 	u8 chip_id;
117812f9e9dSLinus Walleij 	struct blocking_notifier_head event_subscribers;
118fa661258SMattias Wallin 	u8 startup_events[3];
119812f9e9dSLinus Walleij 	bool startup_events_read;
120812f9e9dSLinus Walleij };
121812f9e9dSLinus Walleij 
122812f9e9dSLinus Walleij /**
123812f9e9dSLinus Walleij  * struct ab3100_platform_data
124812f9e9dSLinus Walleij  * Data supplied to initialize board connections to the AB3100
125812f9e9dSLinus Walleij  * @reg_constraints: regulator constraints for target board
126812f9e9dSLinus Walleij  *     the order of these constraints are: LDO A, C, D, E,
127812f9e9dSLinus Walleij  *     F, G, H, K, EXT and BUCK.
128812f9e9dSLinus Walleij  * @reg_initvals: initial values for the regulator registers
129812f9e9dSLinus Walleij  *     plus two sleep settings for LDO E and the BUCK converter.
130812f9e9dSLinus Walleij  *     exactly AB3100_NUM_REGULATORS+2 values must be sent in.
131812f9e9dSLinus Walleij  *     Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
132812f9e9dSLinus Walleij  *     BUCK sleep, LDO D. (LDO D need to be initialized last.)
133812f9e9dSLinus Walleij  * @external_voltage: voltage level of the external regulator.
134812f9e9dSLinus Walleij  */
135812f9e9dSLinus Walleij struct ab3100_platform_data {
136812f9e9dSLinus Walleij 	struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
137812f9e9dSLinus Walleij 	u8 reg_initvals[AB3100_NUM_REGULATORS+2];
138812f9e9dSLinus Walleij 	int external_voltage;
139812f9e9dSLinus Walleij };
140812f9e9dSLinus Walleij 
141812f9e9dSLinus Walleij int ab3100_event_register(struct ab3100 *ab3100,
142812f9e9dSLinus Walleij 			  struct notifier_block *nb);
143812f9e9dSLinus Walleij int ab3100_event_unregister(struct ab3100 *ab3100,
144812f9e9dSLinus Walleij 			    struct notifier_block *nb);
145812f9e9dSLinus Walleij 
146fa661258SMattias Wallin /* AB3550, STR register flags */
147fa661258SMattias Wallin #define AB3550_STR_ONSWA				(0x01)
148fa661258SMattias Wallin #define AB3550_STR_ONSWB				(0x02)
149fa661258SMattias Wallin #define AB3550_STR_ONSWC				(0x04)
150fa661258SMattias Wallin #define AB3550_STR_DCIO					(0x08)
151fa661258SMattias Wallin #define AB3550_STR_BOOT_MODE				(0x10)
152fa661258SMattias Wallin #define AB3550_STR_SIM_OFF				(0x20)
153fa661258SMattias Wallin #define AB3550_STR_BATT_REMOVAL				(0x40)
154fa661258SMattias Wallin #define AB3550_STR_VBUS					(0x80)
155fa661258SMattias Wallin 
156fa661258SMattias Wallin /* Interrupt mask registers */
157fa661258SMattias Wallin #define AB3550_IMR1 0x29
158fa661258SMattias Wallin #define AB3550_IMR2 0x2a
159fa661258SMattias Wallin #define AB3550_IMR3 0x2b
160fa661258SMattias Wallin #define AB3550_IMR4 0x2c
161fa661258SMattias Wallin #define AB3550_IMR5 0x2d
162fa661258SMattias Wallin 
163fa661258SMattias Wallin enum ab3550_devid {
164fa661258SMattias Wallin 	AB3550_DEVID_ADC,
165fa661258SMattias Wallin 	AB3550_DEVID_DAC,
166fa661258SMattias Wallin 	AB3550_DEVID_LEDS,
167fa661258SMattias Wallin 	AB3550_DEVID_POWER,
168fa661258SMattias Wallin 	AB3550_DEVID_REGULATORS,
169fa661258SMattias Wallin 	AB3550_DEVID_SIM,
170fa661258SMattias Wallin 	AB3550_DEVID_UART,
171fa661258SMattias Wallin 	AB3550_DEVID_RTC,
172fa661258SMattias Wallin 	AB3550_DEVID_CHARGER,
173fa661258SMattias Wallin 	AB3550_DEVID_FUELGAUGE,
174fa661258SMattias Wallin 	AB3550_DEVID_VIBRATOR,
175fa661258SMattias Wallin 	AB3550_DEVID_CODEC,
176fa661258SMattias Wallin 	AB3550_NUM_DEVICES,
177fa661258SMattias Wallin };
178fa661258SMattias Wallin 
179fa661258SMattias Wallin /**
180fa661258SMattias Wallin  * struct abx500_init_setting
181fa661258SMattias Wallin  * Initial value of the registers for driver to use during setup.
182fa661258SMattias Wallin  */
183fa661258SMattias Wallin struct abx500_init_settings {
184fa661258SMattias Wallin 	u8 bank;
185fa661258SMattias Wallin 	u8 reg;
186fa661258SMattias Wallin 	u8 setting;
187fa661258SMattias Wallin };
188fa661258SMattias Wallin 
189fa661258SMattias Wallin /**
190fa661258SMattias Wallin  * struct ab3550_platform_data
191fa661258SMattias Wallin  * Data supplied to initialize board connections to the AB3550
192fa661258SMattias Wallin  */
193fa661258SMattias Wallin struct ab3550_platform_data {
194fa661258SMattias Wallin 	struct {unsigned int base; unsigned int count; } irq;
195fa661258SMattias Wallin 	void *dev_data[AB3550_NUM_DEVICES];
1961f235a37SSamuel Ortiz 	size_t dev_data_sz[AB3550_NUM_DEVICES];
197fa661258SMattias Wallin 	struct abx500_init_settings *init_settings;
198fa661258SMattias Wallin 	unsigned int init_settings_sz;
199fa661258SMattias Wallin };
200fa661258SMattias Wallin 
201fa661258SMattias Wallin int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
202fa661258SMattias Wallin 	u8 value);
203fa661258SMattias Wallin int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
204fa661258SMattias Wallin 	u8 *value);
205fa661258SMattias Wallin int abx500_get_register_page_interruptible(struct device *dev, u8 bank,
206fa661258SMattias Wallin 	u8 first_reg, u8 *regvals, u8 numregs);
207fa661258SMattias Wallin int abx500_set_register_page_interruptible(struct device *dev, u8 bank,
208fa661258SMattias Wallin 	u8 first_reg, u8 *regvals, u8 numregs);
209fa661258SMattias Wallin /**
210fa661258SMattias Wallin  * abx500_mask_and_set_register_inerruptible() - Modifies selected bits of a
211fa661258SMattias Wallin  *	target register
212fa661258SMattias Wallin  *
213fa661258SMattias Wallin  * @dev: The AB sub device.
214fa661258SMattias Wallin  * @bank: The i2c bank number.
215fa661258SMattias Wallin  * @bitmask: The bit mask to use.
216fa661258SMattias Wallin  * @bitvalues: The new bit values.
217fa661258SMattias Wallin  *
218fa661258SMattias Wallin  * Updates the value of an AB register:
219fa661258SMattias Wallin  * value -> ((value & ~bitmask) | (bitvalues & bitmask))
220fa661258SMattias Wallin  */
221fa661258SMattias Wallin int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
222fa661258SMattias Wallin 	u8 reg, u8 bitmask, u8 bitvalues);
223fa661258SMattias Wallin int abx500_get_chip_id(struct device *dev);
224fa661258SMattias Wallin int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
225fa661258SMattias Wallin int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);
226fa661258SMattias Wallin 
227fa661258SMattias Wallin struct abx500_ops {
228fa661258SMattias Wallin 	int (*get_chip_id) (struct device *);
229fa661258SMattias Wallin 	int (*get_register) (struct device *, u8, u8, u8 *);
230fa661258SMattias Wallin 	int (*set_register) (struct device *, u8, u8, u8);
231fa661258SMattias Wallin 	int (*get_register_page) (struct device *, u8, u8, u8 *, u8);
232fa661258SMattias Wallin 	int (*set_register_page) (struct device *, u8, u8, u8 *, u8);
233fa661258SMattias Wallin 	int (*mask_and_set_register) (struct device *, u8, u8, u8, u8);
234fa661258SMattias Wallin 	int (*event_registers_startup_state_get) (struct device *, u8 *);
235fa661258SMattias Wallin 	int (*startup_irq_enabled) (struct device *, unsigned int);
236fa661258SMattias Wallin };
237fa661258SMattias Wallin 
238fa661258SMattias Wallin int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops);
239c6252e9cSMark Brown void abx500_remove_ops(struct device *dev);
240812f9e9dSLinus Walleij #endif
241