1abc848c1SLennert Buytenhek /*
2abc848c1SLennert Buytenhek * Marvell MBUS common definitions.
3abc848c1SLennert Buytenhek *
4abc848c1SLennert Buytenhek * Copyright (C) 2008 Marvell Semiconductor
5abc848c1SLennert Buytenhek *
6abc848c1SLennert Buytenhek * This file is licensed under the terms of the GNU General Public
7abc848c1SLennert Buytenhek * License version 2. This program is licensed "as is" without any
8abc848c1SLennert Buytenhek * warranty of any kind, whether express or implied.
9abc848c1SLennert Buytenhek */
10abc848c1SLennert Buytenhek
11abc848c1SLennert Buytenhek #ifndef __LINUX_MBUS_H
12abc848c1SLennert Buytenhek #define __LINUX_MBUS_H
13abc848c1SLennert Buytenhek
14434cec62SStefan Roese #include <linux/errno.h>
15434cec62SStefan Roese
1679d94683SEzequiel Garcia struct resource;
1779d94683SEzequiel Garcia
18abc848c1SLennert Buytenhek struct mbus_dram_target_info
19abc848c1SLennert Buytenhek {
20abc848c1SLennert Buytenhek /*
21abc848c1SLennert Buytenhek * The 4-bit MBUS target ID of the DRAM controller.
22abc848c1SLennert Buytenhek */
23abc848c1SLennert Buytenhek u8 mbus_dram_target_id;
24abc848c1SLennert Buytenhek
25abc848c1SLennert Buytenhek /*
26abc848c1SLennert Buytenhek * The base address, size, and MBUS attribute ID for each
27abc848c1SLennert Buytenhek * of the possible DRAM chip selects. Peripherals are
28abc848c1SLennert Buytenhek * required to support at least 4 decode windows.
29abc848c1SLennert Buytenhek */
30abc848c1SLennert Buytenhek int num_cs;
31abc848c1SLennert Buytenhek struct mbus_dram_window {
32abc848c1SLennert Buytenhek u8 cs_index;
33abc848c1SLennert Buytenhek u8 mbus_attr;
342bbbd963SJan Luebbe u64 base;
352bbbd963SJan Luebbe u64 size;
36abc848c1SLennert Buytenhek } cs[4];
37abc848c1SLennert Buytenhek };
38abc848c1SLennert Buytenhek
39fddddb52SThomas Petazzoni /* Flags for PCI/PCIe address decoding regions */
40fddddb52SThomas Petazzoni #define MVEBU_MBUS_PCI_IO 0x1
41fddddb52SThomas Petazzoni #define MVEBU_MBUS_PCI_MEM 0x2
42fddddb52SThomas Petazzoni #define MVEBU_MBUS_PCI_WA 0x3
43fddddb52SThomas Petazzoni
44fddddb52SThomas Petazzoni /*
45fddddb52SThomas Petazzoni * Magic value that explicits that we don't need a remapping-capable
46fddddb52SThomas Petazzoni * address decoding window.
47fddddb52SThomas Petazzoni */
48fddddb52SThomas Petazzoni #define MVEBU_MBUS_NO_REMAP (0xffffffff)
49fddddb52SThomas Petazzoni
5095b80e0aSThomas Petazzoni /* Maximum size of a mbus window name */
5195b80e0aSThomas Petazzoni #define MVEBU_MBUS_MAX_WINNAME_SZ 32
5295b80e0aSThomas Petazzoni
5363a9332bSAndrew Lunn /*
5463a9332bSAndrew Lunn * The Marvell mbus is to be found only on SOCs from the Orion family
5563a9332bSAndrew Lunn * at the moment. Provide a dummy stub for other architectures.
5663a9332bSAndrew Lunn */
5763a9332bSAndrew Lunn #ifdef CONFIG_PLAT_ORION
5863a9332bSAndrew Lunn extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
59bfa1ce5fSThomas Petazzoni extern const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void);
60434cec62SStefan Roese int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
61434cec62SStefan Roese u8 *attr);
6263a9332bSAndrew Lunn #else
mv_mbus_dram_info(void)6363a9332bSAndrew Lunn static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
6463a9332bSAndrew Lunn {
6563a9332bSAndrew Lunn return NULL;
6663a9332bSAndrew Lunn }
mv_mbus_dram_info_nooverlap(void)67bfa1ce5fSThomas Petazzoni static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
68bfa1ce5fSThomas Petazzoni {
69bfa1ce5fSThomas Petazzoni return NULL;
70bfa1ce5fSThomas Petazzoni }
mvebu_mbus_get_io_win_info(phys_addr_t phyaddr,u32 * size,u8 * target,u8 * attr)71434cec62SStefan Roese static inline int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size,
72434cec62SStefan Roese u8 *target, u8 *attr)
73434cec62SStefan Roese {
74434cec62SStefan Roese /*
75434cec62SStefan Roese * On all ARM32 MVEBU platforms with MBus support, this stub
76434cec62SStefan Roese * function will not get called. The real function from the
77434cec62SStefan Roese * MBus driver is called instead. ARM64 MVEBU platforms like
78434cec62SStefan Roese * the Armada 3700 could use the mv_xor device driver which calls
79434cec62SStefan Roese * into this function
80434cec62SStefan Roese */
81434cec62SStefan Roese return -EINVAL;
82434cec62SStefan Roese }
8363a9332bSAndrew Lunn #endif
84fddddb52SThomas Petazzoni
85603ab573SFlorian Fainelli #ifdef CONFIG_MVEBU_MBUS
86fce7b5aeSBen Dooks int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr);
8779d94683SEzequiel Garcia void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
8879d94683SEzequiel Garcia void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
89f2900aceSMarcin Wojtas int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
906a63b098SThomas Petazzoni int mvebu_mbus_add_window_remap_by_id(unsigned int target,
916a63b098SThomas Petazzoni unsigned int attribute,
926a63b098SThomas Petazzoni phys_addr_t base, size_t size,
936a63b098SThomas Petazzoni phys_addr_t remap);
946a63b098SThomas Petazzoni int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
956a63b098SThomas Petazzoni phys_addr_t base, size_t size);
96fddddb52SThomas Petazzoni int mvebu_mbus_del_window(phys_addr_t base, size_t size);
97fddddb52SThomas Petazzoni int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
98fddddb52SThomas Petazzoni size_t mbus_size, phys_addr_t sdram_phys_base,
99fddddb52SThomas Petazzoni size_t sdram_size);
1005686a1e5SThomas Petazzoni int mvebu_mbus_dt_init(bool is_coherent);
101603ab573SFlorian Fainelli #else
mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr,u8 * target,u8 * attr)102603ab573SFlorian Fainelli static inline int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target,
103603ab573SFlorian Fainelli u8 *attr)
104603ab573SFlorian Fainelli {
105603ab573SFlorian Fainelli return -EINVAL;
106603ab573SFlorian Fainelli }
107603ab573SFlorian Fainelli #endif /* CONFIG_MVEBU_MBUS */
108fddddb52SThomas Petazzoni
109fddddb52SThomas Petazzoni #endif /* __LINUX_MBUS_H */
110