1*8ddde07aSTian Tao /* SPDX-License-Identifier: GPL-2.0-only */ 2*8ddde07aSTian Tao /* 3*8ddde07aSTian Tao * Copyright (C) 2022 HiSilicon Limited. 4*8ddde07aSTian Tao */ 5*8ddde07aSTian Tao 6*8ddde07aSTian Tao #ifndef _KERNEL_DMA_BENCHMARK_H 7*8ddde07aSTian Tao #define _KERNEL_DMA_BENCHMARK_H 8*8ddde07aSTian Tao 9*8ddde07aSTian Tao #define DMA_MAP_BENCHMARK _IOWR('d', 1, struct map_benchmark) 10*8ddde07aSTian Tao #define DMA_MAP_MAX_THREADS 1024 11*8ddde07aSTian Tao #define DMA_MAP_MAX_SECONDS 300 12*8ddde07aSTian Tao #define DMA_MAP_MAX_TRANS_DELAY (10 * NSEC_PER_MSEC) 13*8ddde07aSTian Tao 14*8ddde07aSTian Tao #define DMA_MAP_BIDIRECTIONAL 0 15*8ddde07aSTian Tao #define DMA_MAP_TO_DEVICE 1 16*8ddde07aSTian Tao #define DMA_MAP_FROM_DEVICE 2 17*8ddde07aSTian Tao 18*8ddde07aSTian Tao struct map_benchmark { 19*8ddde07aSTian Tao __u64 avg_map_100ns; /* average map latency in 100ns */ 20*8ddde07aSTian Tao __u64 map_stddev; /* standard deviation of map latency */ 21*8ddde07aSTian Tao __u64 avg_unmap_100ns; /* as above */ 22*8ddde07aSTian Tao __u64 unmap_stddev; 23*8ddde07aSTian Tao __u32 threads; /* how many threads will do map/unmap in parallel */ 24*8ddde07aSTian Tao __u32 seconds; /* how long the test will last */ 25*8ddde07aSTian Tao __s32 node; /* which numa node this benchmark will run on */ 26*8ddde07aSTian Tao __u32 dma_bits; /* DMA addressing capability */ 27*8ddde07aSTian Tao __u32 dma_dir; /* DMA data direction */ 28*8ddde07aSTian Tao __u32 dma_trans_ns; /* time for DMA transmission in ns */ 29*8ddde07aSTian Tao __u32 granule; /* how many PAGE_SIZE will do map/unmap once a time */ 30*8ddde07aSTian Tao }; 31*8ddde07aSTian Tao #endif /* _KERNEL_DMA_BENCHMARK_H */ 32