1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_IRQ_H 3 #define _LINUX_IRQ_H 4 5 /* 6 * Please do not include this file in generic code. There is currently 7 * no requirement for any architecture to implement anything held 8 * within this file. 9 * 10 * Thanks. --rmk 11 */ 12 13 #include <linux/cache.h> 14 #include <linux/spinlock.h> 15 #include <linux/cpumask.h> 16 #include <linux/irqhandler.h> 17 #include <linux/irqreturn.h> 18 #include <linux/irqnr.h> 19 #include <linux/topology.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 23 #include <asm/irq.h> 24 #include <asm/ptrace.h> 25 #include <asm/irq_regs.h> 26 27 struct seq_file; 28 struct module; 29 struct msi_msg; 30 struct irq_affinity_desc; 31 enum irqchip_irq_state; 32 33 /* 34 * IRQ line status. 35 * 36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 37 * 38 * IRQ_TYPE_NONE - default, unspecified type 39 * IRQ_TYPE_EDGE_RISING - rising edge triggered 40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 42 * IRQ_TYPE_LEVEL_HIGH - high level triggered 43 * IRQ_TYPE_LEVEL_LOW - low level triggered 44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 47 * to setup the HW to a sane default (used 48 * by irqdomain map() callbacks to synchronize 49 * the HW state and SW flags for a newly 50 * allocated descriptor). 51 * 52 * IRQ_TYPE_PROBE - Special flag for probing in progress 53 * 54 * Bits which can be modified via irq_set/clear/modify_status_flags() 55 * IRQ_LEVEL - Interrupt is level type. Will be also 56 * updated in the code when the above trigger 57 * bits are modified via irq_set_irq_type() 58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 59 * it from affinity setting 60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 61 * IRQ_NOREQUEST - Interrupt cannot be requested via 62 * request_irq() 63 * IRQ_NOTHREAD - Interrupt cannot be threaded 64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 65 * request/setup_irq() 66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 68 * IRQ_NESTED_THREAD - Interrupt nests into another thread 69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 71 * it from the spurious interrupt detection 72 * mechanism and from core side polling. 73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 74 * IRQ_HIDDEN - Don't show up in /proc/interrupts 75 * IRQ_NO_DEBUG - Exclude from note_interrupt() debugging 76 */ 77 enum { 78 IRQ_TYPE_NONE = 0x00000000, 79 IRQ_TYPE_EDGE_RISING = 0x00000001, 80 IRQ_TYPE_EDGE_FALLING = 0x00000002, 81 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 82 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 83 IRQ_TYPE_LEVEL_LOW = 0x00000008, 84 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 85 IRQ_TYPE_SENSE_MASK = 0x0000000f, 86 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 87 88 IRQ_TYPE_PROBE = 0x00000010, 89 90 IRQ_LEVEL = (1 << 8), 91 IRQ_PER_CPU = (1 << 9), 92 IRQ_NOPROBE = (1 << 10), 93 IRQ_NOREQUEST = (1 << 11), 94 IRQ_NOAUTOEN = (1 << 12), 95 IRQ_NO_BALANCING = (1 << 13), 96 IRQ_MOVE_PCNTXT = (1 << 14), 97 IRQ_NESTED_THREAD = (1 << 15), 98 IRQ_NOTHREAD = (1 << 16), 99 IRQ_PER_CPU_DEVID = (1 << 17), 100 IRQ_IS_POLLED = (1 << 18), 101 IRQ_DISABLE_UNLAZY = (1 << 19), 102 IRQ_HIDDEN = (1 << 20), 103 IRQ_NO_DEBUG = (1 << 21), 104 }; 105 106 #define IRQF_MODIFY_MASK \ 107 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 108 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 109 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 110 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN) 111 112 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 113 114 /* 115 * Return value for chip->irq_set_affinity() 116 * 117 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 118 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity 119 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 120 * support stacked irqchips, which indicates skipping 121 * all descendant irqchips. 122 */ 123 enum { 124 IRQ_SET_MASK_OK = 0, 125 IRQ_SET_MASK_OK_NOCOPY, 126 IRQ_SET_MASK_OK_DONE, 127 }; 128 129 struct msi_desc; 130 struct irq_domain; 131 132 /** 133 * struct irq_common_data - per irq data shared by all irqchips 134 * @state_use_accessors: status information for irq chip functions. 135 * Use accessor functions to deal with it 136 * @node: node index useful for balancing 137 * @handler_data: per-IRQ data for the irq_chip methods 138 * @affinity: IRQ affinity on SMP. If this is an IPI 139 * related irq, then this is the mask of the 140 * CPUs to which an IPI can be sent. 141 * @effective_affinity: The effective IRQ affinity on SMP as some irq 142 * chips do not allow multi CPU destinations. 143 * A subset of @affinity. 144 * @msi_desc: MSI descriptor 145 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. 146 */ 147 struct irq_common_data { 148 unsigned int __private state_use_accessors; 149 #ifdef CONFIG_NUMA 150 unsigned int node; 151 #endif 152 void *handler_data; 153 struct msi_desc *msi_desc; 154 #ifdef CONFIG_SMP 155 cpumask_var_t affinity; 156 #endif 157 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 158 cpumask_var_t effective_affinity; 159 #endif 160 #ifdef CONFIG_GENERIC_IRQ_IPI 161 unsigned int ipi_offset; 162 #endif 163 }; 164 165 /** 166 * struct irq_data - per irq chip data passed down to chip functions 167 * @mask: precomputed bitmask for accessing the chip registers 168 * @irq: interrupt number 169 * @hwirq: hardware interrupt number, local to the interrupt domain 170 * @common: point to data shared by all irqchips 171 * @chip: low level interrupt hardware access 172 * @domain: Interrupt translation domain; responsible for mapping 173 * between hwirq number and linux irq number. 174 * @parent_data: pointer to parent struct irq_data to support hierarchy 175 * irq_domain 176 * @chip_data: platform-specific per-chip private data for the chip 177 * methods, to allow shared chip implementations 178 */ 179 struct irq_data { 180 u32 mask; 181 unsigned int irq; 182 unsigned long hwirq; 183 struct irq_common_data *common; 184 struct irq_chip *chip; 185 struct irq_domain *domain; 186 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 187 struct irq_data *parent_data; 188 #endif 189 void *chip_data; 190 }; 191 192 /* 193 * Bit masks for irq_common_data.state_use_accessors 194 * 195 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 196 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 197 * IRQD_ACTIVATED - Interrupt has already been activated 198 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 199 * IRQD_PER_CPU - Interrupt is per cpu 200 * IRQD_AFFINITY_SET - Interrupt affinity was set 201 * IRQD_LEVEL - Interrupt is level triggered 202 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 203 * from suspend 204 * IRQD_MOVE_PCNTXT - Interrupt can be moved in process 205 * context 206 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 207 * IRQD_IRQ_MASKED - Masked state of the interrupt 208 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 209 * IRQD_WAKEUP_ARMED - Wakeup mode armed 210 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 211 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel 212 * IRQD_IRQ_STARTED - Startup state of the interrupt 213 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity 214 * mask. Applies only to affinity managed irqs. 215 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target 216 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set 217 * IRQD_CAN_RESERVE - Can use reservation mode 218 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change 219 * required 220 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked 221 * from actual interrupt context. 222 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call 223 * irq_chip::irq_set_affinity() when deactivated. 224 * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if 225 * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set. 226 * IRQD_RESEND_WHEN_IN_PROGRESS - Interrupt may fire when already in progress in which 227 * case it must be resent at the next available opportunity. 228 */ 229 enum { 230 IRQD_TRIGGER_MASK = 0xf, 231 IRQD_SETAFFINITY_PENDING = BIT(8), 232 IRQD_ACTIVATED = BIT(9), 233 IRQD_NO_BALANCING = BIT(10), 234 IRQD_PER_CPU = BIT(11), 235 IRQD_AFFINITY_SET = BIT(12), 236 IRQD_LEVEL = BIT(13), 237 IRQD_WAKEUP_STATE = BIT(14), 238 IRQD_MOVE_PCNTXT = BIT(15), 239 IRQD_IRQ_DISABLED = BIT(16), 240 IRQD_IRQ_MASKED = BIT(17), 241 IRQD_IRQ_INPROGRESS = BIT(18), 242 IRQD_WAKEUP_ARMED = BIT(19), 243 IRQD_FORWARDED_TO_VCPU = BIT(20), 244 IRQD_AFFINITY_MANAGED = BIT(21), 245 IRQD_IRQ_STARTED = BIT(22), 246 IRQD_MANAGED_SHUTDOWN = BIT(23), 247 IRQD_SINGLE_TARGET = BIT(24), 248 IRQD_DEFAULT_TRIGGER_SET = BIT(25), 249 IRQD_CAN_RESERVE = BIT(26), 250 IRQD_MSI_NOMASK_QUIRK = BIT(27), 251 IRQD_HANDLE_ENFORCE_IRQCTX = BIT(28), 252 IRQD_AFFINITY_ON_ACTIVATE = BIT(29), 253 IRQD_IRQ_ENABLED_ON_SUSPEND = BIT(30), 254 IRQD_RESEND_WHEN_IN_PROGRESS = BIT(31), 255 }; 256 257 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) 258 259 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 260 { 261 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 262 } 263 264 static inline bool irqd_is_per_cpu(struct irq_data *d) 265 { 266 return __irqd_to_state(d) & IRQD_PER_CPU; 267 } 268 269 static inline bool irqd_can_balance(struct irq_data *d) 270 { 271 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 272 } 273 274 static inline bool irqd_affinity_was_set(struct irq_data *d) 275 { 276 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 277 } 278 279 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 280 { 281 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 282 } 283 284 static inline bool irqd_trigger_type_was_set(struct irq_data *d) 285 { 286 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; 287 } 288 289 static inline u32 irqd_get_trigger_type(struct irq_data *d) 290 { 291 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 292 } 293 294 /* 295 * Must only be called inside irq_chip.irq_set_type() functions or 296 * from the DT/ACPI setup code. 297 */ 298 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 299 { 300 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 301 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 302 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; 303 } 304 305 static inline bool irqd_is_level_type(struct irq_data *d) 306 { 307 return __irqd_to_state(d) & IRQD_LEVEL; 308 } 309 310 /* 311 * Must only be called of irqchip.irq_set_affinity() or low level 312 * hierarchy domain allocation functions. 313 */ 314 static inline void irqd_set_single_target(struct irq_data *d) 315 { 316 __irqd_to_state(d) |= IRQD_SINGLE_TARGET; 317 } 318 319 static inline bool irqd_is_single_target(struct irq_data *d) 320 { 321 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 322 } 323 324 static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d) 325 { 326 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX; 327 } 328 329 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d) 330 { 331 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX; 332 } 333 334 static inline bool irqd_is_enabled_on_suspend(struct irq_data *d) 335 { 336 return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND; 337 } 338 339 static inline bool irqd_is_wakeup_set(struct irq_data *d) 340 { 341 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 342 } 343 344 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 345 { 346 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; 347 } 348 349 static inline bool irqd_irq_disabled(struct irq_data *d) 350 { 351 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 352 } 353 354 static inline bool irqd_irq_masked(struct irq_data *d) 355 { 356 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 357 } 358 359 static inline bool irqd_irq_inprogress(struct irq_data *d) 360 { 361 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 362 } 363 364 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 365 { 366 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 367 } 368 369 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 370 { 371 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 372 } 373 374 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 375 { 376 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 377 } 378 379 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 380 { 381 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 382 } 383 384 static inline bool irqd_affinity_is_managed(struct irq_data *d) 385 { 386 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; 387 } 388 389 static inline bool irqd_is_activated(struct irq_data *d) 390 { 391 return __irqd_to_state(d) & IRQD_ACTIVATED; 392 } 393 394 static inline void irqd_set_activated(struct irq_data *d) 395 { 396 __irqd_to_state(d) |= IRQD_ACTIVATED; 397 } 398 399 static inline void irqd_clr_activated(struct irq_data *d) 400 { 401 __irqd_to_state(d) &= ~IRQD_ACTIVATED; 402 } 403 404 static inline bool irqd_is_started(struct irq_data *d) 405 { 406 return __irqd_to_state(d) & IRQD_IRQ_STARTED; 407 } 408 409 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) 410 { 411 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; 412 } 413 414 static inline void irqd_set_can_reserve(struct irq_data *d) 415 { 416 __irqd_to_state(d) |= IRQD_CAN_RESERVE; 417 } 418 419 static inline void irqd_clr_can_reserve(struct irq_data *d) 420 { 421 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; 422 } 423 424 static inline bool irqd_can_reserve(struct irq_data *d) 425 { 426 return __irqd_to_state(d) & IRQD_CAN_RESERVE; 427 } 428 429 static inline void irqd_set_msi_nomask_quirk(struct irq_data *d) 430 { 431 __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK; 432 } 433 434 static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d) 435 { 436 __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK; 437 } 438 439 static inline bool irqd_msi_nomask_quirk(struct irq_data *d) 440 { 441 return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK; 442 } 443 444 static inline void irqd_set_affinity_on_activate(struct irq_data *d) 445 { 446 __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE; 447 } 448 449 static inline bool irqd_affinity_on_activate(struct irq_data *d) 450 { 451 return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE; 452 } 453 454 static inline void irqd_set_resend_when_in_progress(struct irq_data *d) 455 { 456 __irqd_to_state(d) |= IRQD_RESEND_WHEN_IN_PROGRESS; 457 } 458 459 static inline bool irqd_needs_resend_when_in_progress(struct irq_data *d) 460 { 461 return __irqd_to_state(d) & IRQD_RESEND_WHEN_IN_PROGRESS; 462 } 463 464 #undef __irqd_to_state 465 466 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 467 { 468 return d->hwirq; 469 } 470 471 /** 472 * struct irq_chip - hardware interrupt chip descriptor 473 * 474 * @name: name for /proc/interrupts 475 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 476 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 477 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 478 * @irq_disable: disable the interrupt 479 * @irq_ack: start of a new interrupt 480 * @irq_mask: mask an interrupt source 481 * @irq_mask_ack: ack and mask an interrupt source 482 * @irq_unmask: unmask an interrupt source 483 * @irq_eoi: end of interrupt 484 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force 485 * argument is true, it tells the driver to 486 * unconditionally apply the affinity setting. Sanity 487 * checks against the supplied affinity mask are not 488 * required. This is used for CPU hotplug where the 489 * target CPU is not yet set in the cpu_online_mask. 490 * @irq_retrigger: resend an IRQ to the CPU 491 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 492 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 493 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 494 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 495 * @irq_cpu_online: configure an interrupt source for a secondary CPU 496 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 497 * @irq_suspend: function called from core code on suspend once per 498 * chip, when one or more interrupts are installed 499 * @irq_resume: function called from core code on resume once per chip, 500 * when one ore more interrupts are installed 501 * @irq_pm_shutdown: function called from core code on shutdown once per chip 502 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 503 * @irq_print_chip: optional to print special chip info in show_interrupts 504 * @irq_request_resources: optional to request resources before calling 505 * any other callback related to this irq 506 * @irq_release_resources: optional to release resources acquired with 507 * irq_request_resources 508 * @irq_compose_msi_msg: optional to compose message content for MSI 509 * @irq_write_msi_msg: optional to write message content for MSI 510 * @irq_get_irqchip_state: return the internal state of an interrupt 511 * @irq_set_irqchip_state: set the internal state of a interrupt 512 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 513 * @ipi_send_single: send a single IPI to destination cpus 514 * @ipi_send_mask: send an IPI to destination cpus in cpumask 515 * @irq_nmi_setup: function called from core code before enabling an NMI 516 * @irq_nmi_teardown: function called from core code after disabling an NMI 517 * @flags: chip specific flags 518 */ 519 struct irq_chip { 520 const char *name; 521 unsigned int (*irq_startup)(struct irq_data *data); 522 void (*irq_shutdown)(struct irq_data *data); 523 void (*irq_enable)(struct irq_data *data); 524 void (*irq_disable)(struct irq_data *data); 525 526 void (*irq_ack)(struct irq_data *data); 527 void (*irq_mask)(struct irq_data *data); 528 void (*irq_mask_ack)(struct irq_data *data); 529 void (*irq_unmask)(struct irq_data *data); 530 void (*irq_eoi)(struct irq_data *data); 531 532 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 533 int (*irq_retrigger)(struct irq_data *data); 534 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 535 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 536 537 void (*irq_bus_lock)(struct irq_data *data); 538 void (*irq_bus_sync_unlock)(struct irq_data *data); 539 540 #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE 541 void (*irq_cpu_online)(struct irq_data *data); 542 void (*irq_cpu_offline)(struct irq_data *data); 543 #endif 544 void (*irq_suspend)(struct irq_data *data); 545 void (*irq_resume)(struct irq_data *data); 546 void (*irq_pm_shutdown)(struct irq_data *data); 547 548 void (*irq_calc_mask)(struct irq_data *data); 549 550 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 551 int (*irq_request_resources)(struct irq_data *data); 552 void (*irq_release_resources)(struct irq_data *data); 553 554 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 555 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 556 557 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 558 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 559 560 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 561 562 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); 563 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); 564 565 int (*irq_nmi_setup)(struct irq_data *data); 566 void (*irq_nmi_teardown)(struct irq_data *data); 567 568 unsigned long flags; 569 }; 570 571 /* 572 * irq_chip specific flags 573 * 574 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 575 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 576 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 577 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 578 * when irq enabled 579 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 580 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 581 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 582 * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs 583 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips 584 * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs 585 * in the suspend path if they are in disabled state 586 * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup 587 * IRQCHIP_IMMUTABLE: Don't ever change anything in this chip 588 */ 589 enum { 590 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 591 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 592 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 593 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 594 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 595 IRQCHIP_ONESHOT_SAFE = (1 << 5), 596 IRQCHIP_EOI_THREADED = (1 << 6), 597 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), 598 IRQCHIP_SUPPORTS_NMI = (1 << 8), 599 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), 600 IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10), 601 IRQCHIP_IMMUTABLE = (1 << 11), 602 }; 603 604 #include <linux/irqdesc.h> 605 606 /* 607 * Pick up the arch-dependent methods: 608 */ 609 #include <asm/hw_irq.h> 610 611 #ifndef NR_IRQS_LEGACY 612 # define NR_IRQS_LEGACY 0 613 #endif 614 615 #ifndef ARCH_IRQ_INIT_FLAGS 616 # define ARCH_IRQ_INIT_FLAGS 0 617 #endif 618 619 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 620 621 struct irqaction; 622 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 623 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 624 625 #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE 626 extern void irq_cpu_online(void); 627 extern void irq_cpu_offline(void); 628 #endif 629 extern int irq_set_affinity_locked(struct irq_data *data, 630 const struct cpumask *cpumask, bool force); 631 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 632 633 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) 634 extern void irq_migrate_all_off_this_cpu(void); 635 extern int irq_affinity_online_cpu(unsigned int cpu); 636 #else 637 # define irq_affinity_online_cpu NULL 638 #endif 639 640 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 641 void __irq_move_irq(struct irq_data *data); 642 static inline void irq_move_irq(struct irq_data *data) 643 { 644 if (unlikely(irqd_is_setaffinity_pending(data))) 645 __irq_move_irq(data); 646 } 647 void irq_move_masked_irq(struct irq_data *data); 648 void irq_force_complete_move(struct irq_desc *desc); 649 #else 650 static inline void irq_move_irq(struct irq_data *data) { } 651 static inline void irq_move_masked_irq(struct irq_data *data) { } 652 static inline void irq_force_complete_move(struct irq_desc *desc) { } 653 #endif 654 655 extern int no_irq_affinity; 656 657 #ifdef CONFIG_HARDIRQS_SW_RESEND 658 int irq_set_parent(int irq, int parent_irq); 659 #else 660 static inline int irq_set_parent(int irq, int parent_irq) 661 { 662 return 0; 663 } 664 #endif 665 666 /* 667 * Built-in IRQ handlers for various IRQ types, 668 * callable via desc->handle_irq() 669 */ 670 extern void handle_level_irq(struct irq_desc *desc); 671 extern void handle_fasteoi_irq(struct irq_desc *desc); 672 extern void handle_edge_irq(struct irq_desc *desc); 673 extern void handle_edge_eoi_irq(struct irq_desc *desc); 674 extern void handle_simple_irq(struct irq_desc *desc); 675 extern void handle_untracked_irq(struct irq_desc *desc); 676 extern void handle_percpu_irq(struct irq_desc *desc); 677 extern void handle_percpu_devid_irq(struct irq_desc *desc); 678 extern void handle_bad_irq(struct irq_desc *desc); 679 extern void handle_nested_irq(unsigned int irq); 680 681 extern void handle_fasteoi_nmi(struct irq_desc *desc); 682 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc); 683 684 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 685 extern int irq_chip_pm_get(struct irq_data *data); 686 extern int irq_chip_pm_put(struct irq_data *data); 687 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 688 extern void handle_fasteoi_ack_irq(struct irq_desc *desc); 689 extern void handle_fasteoi_mask_irq(struct irq_desc *desc); 690 extern int irq_chip_set_parent_state(struct irq_data *data, 691 enum irqchip_irq_state which, 692 bool val); 693 extern int irq_chip_get_parent_state(struct irq_data *data, 694 enum irqchip_irq_state which, 695 bool *state); 696 extern void irq_chip_enable_parent(struct irq_data *data); 697 extern void irq_chip_disable_parent(struct irq_data *data); 698 extern void irq_chip_ack_parent(struct irq_data *data); 699 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 700 extern void irq_chip_mask_parent(struct irq_data *data); 701 extern void irq_chip_mask_ack_parent(struct irq_data *data); 702 extern void irq_chip_unmask_parent(struct irq_data *data); 703 extern void irq_chip_eoi_parent(struct irq_data *data); 704 extern int irq_chip_set_affinity_parent(struct irq_data *data, 705 const struct cpumask *dest, 706 bool force); 707 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 708 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 709 void *vcpu_info); 710 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 711 extern int irq_chip_request_resources_parent(struct irq_data *data); 712 extern void irq_chip_release_resources_parent(struct irq_data *data); 713 #endif 714 715 /* Handling of unhandled and spurious interrupts: */ 716 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 717 718 719 /* Enable/disable irq debugging output: */ 720 extern int noirqdebug_setup(char *str); 721 722 /* Checks whether the interrupt can be requested by request_irq(): */ 723 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 724 725 /* Dummy irq-chip implementations: */ 726 extern struct irq_chip no_irq_chip; 727 extern struct irq_chip dummy_irq_chip; 728 729 extern void 730 irq_set_chip_and_handler_name(unsigned int irq, const struct irq_chip *chip, 731 irq_flow_handler_t handle, const char *name); 732 733 static inline void irq_set_chip_and_handler(unsigned int irq, 734 const struct irq_chip *chip, 735 irq_flow_handler_t handle) 736 { 737 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 738 } 739 740 extern int irq_set_percpu_devid(unsigned int irq); 741 extern int irq_set_percpu_devid_partition(unsigned int irq, 742 const struct cpumask *affinity); 743 extern int irq_get_percpu_devid_partition(unsigned int irq, 744 struct cpumask *affinity); 745 746 extern void 747 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 748 const char *name); 749 750 static inline void 751 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 752 { 753 __irq_set_handler(irq, handle, 0, NULL); 754 } 755 756 /* 757 * Set a highlevel chained flow handler for a given IRQ. 758 * (a chained handler is automatically enabled and set to 759 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 760 */ 761 static inline void 762 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 763 { 764 __irq_set_handler(irq, handle, 1, NULL); 765 } 766 767 /* 768 * Set a highlevel chained flow handler and its data for a given IRQ. 769 * (a chained handler is automatically enabled and set to 770 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 771 */ 772 void 773 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 774 void *data); 775 776 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 777 778 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 779 { 780 irq_modify_status(irq, 0, set); 781 } 782 783 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 784 { 785 irq_modify_status(irq, clr, 0); 786 } 787 788 static inline void irq_set_noprobe(unsigned int irq) 789 { 790 irq_modify_status(irq, 0, IRQ_NOPROBE); 791 } 792 793 static inline void irq_set_probe(unsigned int irq) 794 { 795 irq_modify_status(irq, IRQ_NOPROBE, 0); 796 } 797 798 static inline void irq_set_nothread(unsigned int irq) 799 { 800 irq_modify_status(irq, 0, IRQ_NOTHREAD); 801 } 802 803 static inline void irq_set_thread(unsigned int irq) 804 { 805 irq_modify_status(irq, IRQ_NOTHREAD, 0); 806 } 807 808 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 809 { 810 if (nest) 811 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 812 else 813 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 814 } 815 816 static inline void irq_set_percpu_devid_flags(unsigned int irq) 817 { 818 irq_set_status_flags(irq, 819 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 820 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 821 } 822 823 /* Set/get chip/data for an IRQ: */ 824 extern int irq_set_chip(unsigned int irq, const struct irq_chip *chip); 825 extern int irq_set_handler_data(unsigned int irq, void *data); 826 extern int irq_set_chip_data(unsigned int irq, void *data); 827 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 828 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 829 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 830 struct msi_desc *entry); 831 extern struct irq_data *irq_get_irq_data(unsigned int irq); 832 833 static inline struct irq_chip *irq_get_chip(unsigned int irq) 834 { 835 struct irq_data *d = irq_get_irq_data(irq); 836 return d ? d->chip : NULL; 837 } 838 839 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 840 { 841 return d->chip; 842 } 843 844 static inline void *irq_get_chip_data(unsigned int irq) 845 { 846 struct irq_data *d = irq_get_irq_data(irq); 847 return d ? d->chip_data : NULL; 848 } 849 850 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 851 { 852 return d->chip_data; 853 } 854 855 static inline void *irq_get_handler_data(unsigned int irq) 856 { 857 struct irq_data *d = irq_get_irq_data(irq); 858 return d ? d->common->handler_data : NULL; 859 } 860 861 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 862 { 863 return d->common->handler_data; 864 } 865 866 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 867 { 868 struct irq_data *d = irq_get_irq_data(irq); 869 return d ? d->common->msi_desc : NULL; 870 } 871 872 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 873 { 874 return d->common->msi_desc; 875 } 876 877 static inline u32 irq_get_trigger_type(unsigned int irq) 878 { 879 struct irq_data *d = irq_get_irq_data(irq); 880 return d ? irqd_get_trigger_type(d) : 0; 881 } 882 883 static inline int irq_common_data_get_node(struct irq_common_data *d) 884 { 885 #ifdef CONFIG_NUMA 886 return d->node; 887 #else 888 return 0; 889 #endif 890 } 891 892 static inline int irq_data_get_node(struct irq_data *d) 893 { 894 return irq_common_data_get_node(d->common); 895 } 896 897 static inline 898 const struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 899 { 900 #ifdef CONFIG_SMP 901 return d->common->affinity; 902 #else 903 return cpumask_of(0); 904 #endif 905 } 906 907 static inline void irq_data_update_affinity(struct irq_data *d, 908 const struct cpumask *m) 909 { 910 #ifdef CONFIG_SMP 911 cpumask_copy(d->common->affinity, m); 912 #endif 913 } 914 915 static inline const struct cpumask *irq_get_affinity_mask(int irq) 916 { 917 struct irq_data *d = irq_get_irq_data(irq); 918 919 return d ? irq_data_get_affinity_mask(d) : NULL; 920 } 921 922 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 923 static inline 924 const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 925 { 926 return d->common->effective_affinity; 927 } 928 static inline void irq_data_update_effective_affinity(struct irq_data *d, 929 const struct cpumask *m) 930 { 931 cpumask_copy(d->common->effective_affinity, m); 932 } 933 #else 934 static inline void irq_data_update_effective_affinity(struct irq_data *d, 935 const struct cpumask *m) 936 { 937 } 938 static inline 939 const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 940 { 941 return irq_data_get_affinity_mask(d); 942 } 943 #endif 944 945 static inline 946 const struct cpumask *irq_get_effective_affinity_mask(unsigned int irq) 947 { 948 struct irq_data *d = irq_get_irq_data(irq); 949 950 return d ? irq_data_get_effective_affinity_mask(d) : NULL; 951 } 952 953 unsigned int arch_dynirq_lower_bound(unsigned int from); 954 955 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 956 struct module *owner, 957 const struct irq_affinity_desc *affinity); 958 959 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, 960 unsigned int cnt, int node, struct module *owner, 961 const struct irq_affinity_desc *affinity); 962 963 /* use macros to avoid needing export.h for THIS_MODULE */ 964 #define irq_alloc_descs(irq, from, cnt, node) \ 965 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) 966 967 #define irq_alloc_desc(node) \ 968 irq_alloc_descs(-1, 1, 1, node) 969 970 #define irq_alloc_desc_at(at, node) \ 971 irq_alloc_descs(at, at, 1, node) 972 973 #define irq_alloc_desc_from(from, node) \ 974 irq_alloc_descs(-1, from, 1, node) 975 976 #define irq_alloc_descs_from(from, cnt, node) \ 977 irq_alloc_descs(-1, from, cnt, node) 978 979 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ 980 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) 981 982 #define devm_irq_alloc_desc(dev, node) \ 983 devm_irq_alloc_descs(dev, -1, 1, 1, node) 984 985 #define devm_irq_alloc_desc_at(dev, at, node) \ 986 devm_irq_alloc_descs(dev, at, at, 1, node) 987 988 #define devm_irq_alloc_desc_from(dev, from, node) \ 989 devm_irq_alloc_descs(dev, -1, from, 1, node) 990 991 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ 992 devm_irq_alloc_descs(dev, -1, from, cnt, node) 993 994 void irq_free_descs(unsigned int irq, unsigned int cnt); 995 static inline void irq_free_desc(unsigned int irq) 996 { 997 irq_free_descs(irq, 1); 998 } 999 1000 #ifdef CONFIG_GENERIC_IRQ_LEGACY 1001 void irq_init_desc(unsigned int irq); 1002 #endif 1003 1004 /** 1005 * struct irq_chip_regs - register offsets for struct irq_gci 1006 * @enable: Enable register offset to reg_base 1007 * @disable: Disable register offset to reg_base 1008 * @mask: Mask register offset to reg_base 1009 * @ack: Ack register offset to reg_base 1010 * @eoi: Eoi register offset to reg_base 1011 * @type: Type configuration register offset to reg_base 1012 * @polarity: Polarity configuration register offset to reg_base 1013 */ 1014 struct irq_chip_regs { 1015 unsigned long enable; 1016 unsigned long disable; 1017 unsigned long mask; 1018 unsigned long ack; 1019 unsigned long eoi; 1020 unsigned long type; 1021 unsigned long polarity; 1022 }; 1023 1024 /** 1025 * struct irq_chip_type - Generic interrupt chip instance for a flow type 1026 * @chip: The real interrupt chip which provides the callbacks 1027 * @regs: Register offsets for this chip 1028 * @handler: Flow handler associated with this chip 1029 * @type: Chip can handle these flow types 1030 * @mask_cache_priv: Cached mask register private to the chip type 1031 * @mask_cache: Pointer to cached mask register 1032 * 1033 * A irq_generic_chip can have several instances of irq_chip_type when 1034 * it requires different functions and register offsets for different 1035 * flow types. 1036 */ 1037 struct irq_chip_type { 1038 struct irq_chip chip; 1039 struct irq_chip_regs regs; 1040 irq_flow_handler_t handler; 1041 u32 type; 1042 u32 mask_cache_priv; 1043 u32 *mask_cache; 1044 }; 1045 1046 /** 1047 * struct irq_chip_generic - Generic irq chip data structure 1048 * @lock: Lock to protect register and cache data access 1049 * @reg_base: Register base address (virtual) 1050 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 1051 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 1052 * @suspend: Function called from core code on suspend once per 1053 * chip; can be useful instead of irq_chip::suspend to 1054 * handle chip details even when no interrupts are in use 1055 * @resume: Function called from core code on resume once per chip; 1056 * can be useful instead of irq_chip::suspend to handle 1057 * chip details even when no interrupts are in use 1058 * @irq_base: Interrupt base nr for this chip 1059 * @irq_cnt: Number of interrupts handled by this chip 1060 * @mask_cache: Cached mask register shared between all chip types 1061 * @type_cache: Cached type register 1062 * @polarity_cache: Cached polarity register 1063 * @wake_enabled: Interrupt can wakeup from suspend 1064 * @wake_active: Interrupt is marked as an wakeup from suspend source 1065 * @num_ct: Number of available irq_chip_type instances (usually 1) 1066 * @private: Private data for non generic chip callbacks 1067 * @installed: bitfield to denote installed interrupts 1068 * @unused: bitfield to denote unused interrupts 1069 * @domain: irq domain pointer 1070 * @list: List head for keeping track of instances 1071 * @chip_types: Array of interrupt irq_chip_types 1072 * 1073 * Note, that irq_chip_generic can have multiple irq_chip_type 1074 * implementations which can be associated to a particular irq line of 1075 * an irq_chip_generic instance. That allows to share and protect 1076 * state in an irq_chip_generic instance when we need to implement 1077 * different flow mechanisms (level/edge) for it. 1078 */ 1079 struct irq_chip_generic { 1080 raw_spinlock_t lock; 1081 void __iomem *reg_base; 1082 u32 (*reg_readl)(void __iomem *addr); 1083 void (*reg_writel)(u32 val, void __iomem *addr); 1084 void (*suspend)(struct irq_chip_generic *gc); 1085 void (*resume)(struct irq_chip_generic *gc); 1086 unsigned int irq_base; 1087 unsigned int irq_cnt; 1088 u32 mask_cache; 1089 u32 type_cache; 1090 u32 polarity_cache; 1091 u32 wake_enabled; 1092 u32 wake_active; 1093 unsigned int num_ct; 1094 void *private; 1095 unsigned long installed; 1096 unsigned long unused; 1097 struct irq_domain *domain; 1098 struct list_head list; 1099 struct irq_chip_type chip_types[]; 1100 }; 1101 1102 /** 1103 * enum irq_gc_flags - Initialization flags for generic irq chips 1104 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 1105 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 1106 * irq chips which need to call irq_set_wake() on 1107 * the parent irq. Usually GPIO implementations 1108 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 1109 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 1110 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 1111 */ 1112 enum irq_gc_flags { 1113 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 1114 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 1115 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 1116 IRQ_GC_NO_MASK = 1 << 3, 1117 IRQ_GC_BE_IO = 1 << 4, 1118 }; 1119 1120 /* 1121 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 1122 * @irqs_per_chip: Number of interrupts per chip 1123 * @num_chips: Number of chips 1124 * @irq_flags_to_set: IRQ* flags to set on irq setup 1125 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 1126 * @gc_flags: Generic chip specific setup flags 1127 * @gc: Array of pointers to generic interrupt chips 1128 */ 1129 struct irq_domain_chip_generic { 1130 unsigned int irqs_per_chip; 1131 unsigned int num_chips; 1132 unsigned int irq_flags_to_clear; 1133 unsigned int irq_flags_to_set; 1134 enum irq_gc_flags gc_flags; 1135 struct irq_chip_generic *gc[]; 1136 }; 1137 1138 /* Generic chip callback functions */ 1139 void irq_gc_noop(struct irq_data *d); 1140 void irq_gc_mask_disable_reg(struct irq_data *d); 1141 void irq_gc_mask_set_bit(struct irq_data *d); 1142 void irq_gc_mask_clr_bit(struct irq_data *d); 1143 void irq_gc_unmask_enable_reg(struct irq_data *d); 1144 void irq_gc_ack_set_bit(struct irq_data *d); 1145 void irq_gc_ack_clr_bit(struct irq_data *d); 1146 void irq_gc_mask_disable_and_ack_set(struct irq_data *d); 1147 void irq_gc_eoi(struct irq_data *d); 1148 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 1149 1150 /* Setup functions for irq_chip_generic */ 1151 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 1152 irq_hw_number_t hw_irq); 1153 void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq); 1154 struct irq_chip_generic * 1155 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 1156 void __iomem *reg_base, irq_flow_handler_t handler); 1157 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 1158 enum irq_gc_flags flags, unsigned int clr, 1159 unsigned int set); 1160 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 1161 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 1162 unsigned int clr, unsigned int set); 1163 1164 struct irq_chip_generic * 1165 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, 1166 unsigned int irq_base, void __iomem *reg_base, 1167 irq_flow_handler_t handler); 1168 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, 1169 u32 msk, enum irq_gc_flags flags, 1170 unsigned int clr, unsigned int set); 1171 1172 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 1173 1174 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 1175 int num_ct, const char *name, 1176 irq_flow_handler_t handler, 1177 unsigned int clr, unsigned int set, 1178 enum irq_gc_flags flags); 1179 1180 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ 1181 handler, clr, set, flags) \ 1182 ({ \ 1183 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ 1184 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ 1185 handler, clr, set, flags); \ 1186 }) 1187 1188 static inline void irq_free_generic_chip(struct irq_chip_generic *gc) 1189 { 1190 kfree(gc); 1191 } 1192 1193 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, 1194 u32 msk, unsigned int clr, 1195 unsigned int set) 1196 { 1197 irq_remove_generic_chip(gc, msk, clr, set); 1198 irq_free_generic_chip(gc); 1199 } 1200 1201 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 1202 { 1203 return container_of(d->chip, struct irq_chip_type, chip); 1204 } 1205 1206 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 1207 1208 #ifdef CONFIG_SMP 1209 static inline void irq_gc_lock(struct irq_chip_generic *gc) 1210 { 1211 raw_spin_lock(&gc->lock); 1212 } 1213 1214 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 1215 { 1216 raw_spin_unlock(&gc->lock); 1217 } 1218 #else 1219 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 1220 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 1221 #endif 1222 1223 /* 1224 * The irqsave variants are for usage in non interrupt code. Do not use 1225 * them in irq_chip callbacks. Use irq_gc_lock() instead. 1226 */ 1227 #define irq_gc_lock_irqsave(gc, flags) \ 1228 raw_spin_lock_irqsave(&(gc)->lock, flags) 1229 1230 #define irq_gc_unlock_irqrestore(gc, flags) \ 1231 raw_spin_unlock_irqrestore(&(gc)->lock, flags) 1232 1233 static inline void irq_reg_writel(struct irq_chip_generic *gc, 1234 u32 val, int reg_offset) 1235 { 1236 if (gc->reg_writel) 1237 gc->reg_writel(val, gc->reg_base + reg_offset); 1238 else 1239 writel(val, gc->reg_base + reg_offset); 1240 } 1241 1242 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 1243 int reg_offset) 1244 { 1245 if (gc->reg_readl) 1246 return gc->reg_readl(gc->reg_base + reg_offset); 1247 else 1248 return readl(gc->reg_base + reg_offset); 1249 } 1250 1251 struct irq_matrix; 1252 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, 1253 unsigned int alloc_start, 1254 unsigned int alloc_end); 1255 void irq_matrix_online(struct irq_matrix *m); 1256 void irq_matrix_offline(struct irq_matrix *m); 1257 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); 1258 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); 1259 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); 1260 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk, 1261 unsigned int *mapped_cpu); 1262 void irq_matrix_reserve(struct irq_matrix *m); 1263 void irq_matrix_remove_reserved(struct irq_matrix *m); 1264 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, 1265 bool reserved, unsigned int *mapped_cpu); 1266 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, 1267 unsigned int bit, bool managed); 1268 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); 1269 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); 1270 unsigned int irq_matrix_allocated(struct irq_matrix *m); 1271 unsigned int irq_matrix_reserved(struct irq_matrix *m); 1272 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); 1273 1274 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ 1275 #define INVALID_HWIRQ (~0UL) 1276 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); 1277 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); 1278 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); 1279 int ipi_send_single(unsigned int virq, unsigned int cpu); 1280 int ipi_send_mask(unsigned int virq, const struct cpumask *dest); 1281 1282 void ipi_mux_process(void); 1283 int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu)); 1284 1285 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 1286 /* 1287 * Registers a generic IRQ handling function as the top-level IRQ handler in 1288 * the system, which is generally the first C code called from an assembly 1289 * architecture-specific interrupt handler. 1290 * 1291 * Returns 0 on success, or -EBUSY if an IRQ handler has already been 1292 * registered. 1293 */ 1294 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); 1295 1296 /* 1297 * Allows interrupt handlers to find the irqchip that's been registered as the 1298 * top-level IRQ handler. 1299 */ 1300 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; 1301 asmlinkage void generic_handle_arch_irq(struct pt_regs *regs); 1302 #else 1303 #ifndef set_handle_irq 1304 #define set_handle_irq(handle_irq) \ 1305 do { \ 1306 (void)handle_irq; \ 1307 WARN_ON(1); \ 1308 } while (0) 1309 #endif 1310 #endif 1311 1312 #endif /* _LINUX_IRQ_H */ 1313