1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_IRQ_H 3 #define _LINUX_IRQ_H 4 5 /* 6 * Please do not include this file in generic code. There is currently 7 * no requirement for any architecture to implement anything held 8 * within this file. 9 * 10 * Thanks. --rmk 11 */ 12 13 #include <linux/cache.h> 14 #include <linux/spinlock.h> 15 #include <linux/cpumask.h> 16 #include <linux/irqhandler.h> 17 #include <linux/irqreturn.h> 18 #include <linux/irqnr.h> 19 #include <linux/topology.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 23 #include <asm/irq.h> 24 #include <asm/ptrace.h> 25 #include <asm/irq_regs.h> 26 27 struct seq_file; 28 struct module; 29 struct msi_msg; 30 struct irq_affinity_desc; 31 enum irqchip_irq_state; 32 33 /* 34 * IRQ line status. 35 * 36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 37 * 38 * IRQ_TYPE_NONE - default, unspecified type 39 * IRQ_TYPE_EDGE_RISING - rising edge triggered 40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 42 * IRQ_TYPE_LEVEL_HIGH - high level triggered 43 * IRQ_TYPE_LEVEL_LOW - low level triggered 44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 47 * to setup the HW to a sane default (used 48 * by irqdomain map() callbacks to synchronize 49 * the HW state and SW flags for a newly 50 * allocated descriptor). 51 * 52 * IRQ_TYPE_PROBE - Special flag for probing in progress 53 * 54 * Bits which can be modified via irq_set/clear/modify_status_flags() 55 * IRQ_LEVEL - Interrupt is level type. Will be also 56 * updated in the code when the above trigger 57 * bits are modified via irq_set_irq_type() 58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 59 * it from affinity setting 60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 61 * IRQ_NOREQUEST - Interrupt cannot be requested via 62 * request_irq() 63 * IRQ_NOTHREAD - Interrupt cannot be threaded 64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 65 * request/setup_irq() 66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 68 * IRQ_NESTED_THREAD - Interrupt nests into another thread 69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 71 * it from the spurious interrupt detection 72 * mechanism and from core side polling. 73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 74 */ 75 enum { 76 IRQ_TYPE_NONE = 0x00000000, 77 IRQ_TYPE_EDGE_RISING = 0x00000001, 78 IRQ_TYPE_EDGE_FALLING = 0x00000002, 79 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 80 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 81 IRQ_TYPE_LEVEL_LOW = 0x00000008, 82 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 83 IRQ_TYPE_SENSE_MASK = 0x0000000f, 84 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 85 86 IRQ_TYPE_PROBE = 0x00000010, 87 88 IRQ_LEVEL = (1 << 8), 89 IRQ_PER_CPU = (1 << 9), 90 IRQ_NOPROBE = (1 << 10), 91 IRQ_NOREQUEST = (1 << 11), 92 IRQ_NOAUTOEN = (1 << 12), 93 IRQ_NO_BALANCING = (1 << 13), 94 IRQ_MOVE_PCNTXT = (1 << 14), 95 IRQ_NESTED_THREAD = (1 << 15), 96 IRQ_NOTHREAD = (1 << 16), 97 IRQ_PER_CPU_DEVID = (1 << 17), 98 IRQ_IS_POLLED = (1 << 18), 99 IRQ_DISABLE_UNLAZY = (1 << 19), 100 }; 101 102 #define IRQF_MODIFY_MASK \ 103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 106 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) 107 108 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 109 110 /* 111 * Return value for chip->irq_set_affinity() 112 * 113 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity 115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 116 * support stacked irqchips, which indicates skipping 117 * all descendent irqchips. 118 */ 119 enum { 120 IRQ_SET_MASK_OK = 0, 121 IRQ_SET_MASK_OK_NOCOPY, 122 IRQ_SET_MASK_OK_DONE, 123 }; 124 125 struct msi_desc; 126 struct irq_domain; 127 128 /** 129 * struct irq_common_data - per irq data shared by all irqchips 130 * @state_use_accessors: status information for irq chip functions. 131 * Use accessor functions to deal with it 132 * @node: node index useful for balancing 133 * @handler_data: per-IRQ data for the irq_chip methods 134 * @affinity: IRQ affinity on SMP. If this is an IPI 135 * related irq, then this is the mask of the 136 * CPUs to which an IPI can be sent. 137 * @effective_affinity: The effective IRQ affinity on SMP as some irq 138 * chips do not allow multi CPU destinations. 139 * A subset of @affinity. 140 * @msi_desc: MSI descriptor 141 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. 142 */ 143 struct irq_common_data { 144 unsigned int __private state_use_accessors; 145 #ifdef CONFIG_NUMA 146 unsigned int node; 147 #endif 148 void *handler_data; 149 struct msi_desc *msi_desc; 150 cpumask_var_t affinity; 151 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 152 cpumask_var_t effective_affinity; 153 #endif 154 #ifdef CONFIG_GENERIC_IRQ_IPI 155 unsigned int ipi_offset; 156 #endif 157 }; 158 159 /** 160 * struct irq_data - per irq chip data passed down to chip functions 161 * @mask: precomputed bitmask for accessing the chip registers 162 * @irq: interrupt number 163 * @hwirq: hardware interrupt number, local to the interrupt domain 164 * @common: point to data shared by all irqchips 165 * @chip: low level interrupt hardware access 166 * @domain: Interrupt translation domain; responsible for mapping 167 * between hwirq number and linux irq number. 168 * @parent_data: pointer to parent struct irq_data to support hierarchy 169 * irq_domain 170 * @chip_data: platform-specific per-chip private data for the chip 171 * methods, to allow shared chip implementations 172 */ 173 struct irq_data { 174 u32 mask; 175 unsigned int irq; 176 unsigned long hwirq; 177 struct irq_common_data *common; 178 struct irq_chip *chip; 179 struct irq_domain *domain; 180 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 181 struct irq_data *parent_data; 182 #endif 183 void *chip_data; 184 }; 185 186 /* 187 * Bit masks for irq_common_data.state_use_accessors 188 * 189 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 190 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 191 * IRQD_ACTIVATED - Interrupt has already been activated 192 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 193 * IRQD_PER_CPU - Interrupt is per cpu 194 * IRQD_AFFINITY_SET - Interrupt affinity was set 195 * IRQD_LEVEL - Interrupt is level triggered 196 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 197 * from suspend 198 * IRQD_MOVE_PCNTXT - Interrupt can be moved in process 199 * context 200 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 201 * IRQD_IRQ_MASKED - Masked state of the interrupt 202 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 203 * IRQD_WAKEUP_ARMED - Wakeup mode armed 204 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 205 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel 206 * IRQD_IRQ_STARTED - Startup state of the interrupt 207 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity 208 * mask. Applies only to affinity managed irqs. 209 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target 210 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set 211 * IRQD_CAN_RESERVE - Can use reservation mode 212 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change 213 * required 214 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked 215 * from actual interrupt context. 216 */ 217 enum { 218 IRQD_TRIGGER_MASK = 0xf, 219 IRQD_SETAFFINITY_PENDING = (1 << 8), 220 IRQD_ACTIVATED = (1 << 9), 221 IRQD_NO_BALANCING = (1 << 10), 222 IRQD_PER_CPU = (1 << 11), 223 IRQD_AFFINITY_SET = (1 << 12), 224 IRQD_LEVEL = (1 << 13), 225 IRQD_WAKEUP_STATE = (1 << 14), 226 IRQD_MOVE_PCNTXT = (1 << 15), 227 IRQD_IRQ_DISABLED = (1 << 16), 228 IRQD_IRQ_MASKED = (1 << 17), 229 IRQD_IRQ_INPROGRESS = (1 << 18), 230 IRQD_WAKEUP_ARMED = (1 << 19), 231 IRQD_FORWARDED_TO_VCPU = (1 << 20), 232 IRQD_AFFINITY_MANAGED = (1 << 21), 233 IRQD_IRQ_STARTED = (1 << 22), 234 IRQD_MANAGED_SHUTDOWN = (1 << 23), 235 IRQD_SINGLE_TARGET = (1 << 24), 236 IRQD_DEFAULT_TRIGGER_SET = (1 << 25), 237 IRQD_CAN_RESERVE = (1 << 26), 238 IRQD_MSI_NOMASK_QUIRK = (1 << 27), 239 IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28), 240 }; 241 242 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) 243 244 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 245 { 246 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 247 } 248 249 static inline bool irqd_is_per_cpu(struct irq_data *d) 250 { 251 return __irqd_to_state(d) & IRQD_PER_CPU; 252 } 253 254 static inline bool irqd_can_balance(struct irq_data *d) 255 { 256 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 257 } 258 259 static inline bool irqd_affinity_was_set(struct irq_data *d) 260 { 261 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 262 } 263 264 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 265 { 266 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 267 } 268 269 static inline bool irqd_trigger_type_was_set(struct irq_data *d) 270 { 271 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; 272 } 273 274 static inline u32 irqd_get_trigger_type(struct irq_data *d) 275 { 276 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 277 } 278 279 /* 280 * Must only be called inside irq_chip.irq_set_type() functions or 281 * from the DT/ACPI setup code. 282 */ 283 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 284 { 285 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 286 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 287 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; 288 } 289 290 static inline bool irqd_is_level_type(struct irq_data *d) 291 { 292 return __irqd_to_state(d) & IRQD_LEVEL; 293 } 294 295 /* 296 * Must only be called of irqchip.irq_set_affinity() or low level 297 * hieararchy domain allocation functions. 298 */ 299 static inline void irqd_set_single_target(struct irq_data *d) 300 { 301 __irqd_to_state(d) |= IRQD_SINGLE_TARGET; 302 } 303 304 static inline bool irqd_is_single_target(struct irq_data *d) 305 { 306 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 307 } 308 309 static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d) 310 { 311 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX; 312 } 313 314 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d) 315 { 316 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX; 317 } 318 319 static inline bool irqd_is_wakeup_set(struct irq_data *d) 320 { 321 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 322 } 323 324 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 325 { 326 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; 327 } 328 329 static inline bool irqd_irq_disabled(struct irq_data *d) 330 { 331 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 332 } 333 334 static inline bool irqd_irq_masked(struct irq_data *d) 335 { 336 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 337 } 338 339 static inline bool irqd_irq_inprogress(struct irq_data *d) 340 { 341 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 342 } 343 344 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 345 { 346 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 347 } 348 349 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 350 { 351 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 352 } 353 354 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 355 { 356 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 357 } 358 359 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 360 { 361 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 362 } 363 364 static inline bool irqd_affinity_is_managed(struct irq_data *d) 365 { 366 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; 367 } 368 369 static inline bool irqd_is_activated(struct irq_data *d) 370 { 371 return __irqd_to_state(d) & IRQD_ACTIVATED; 372 } 373 374 static inline void irqd_set_activated(struct irq_data *d) 375 { 376 __irqd_to_state(d) |= IRQD_ACTIVATED; 377 } 378 379 static inline void irqd_clr_activated(struct irq_data *d) 380 { 381 __irqd_to_state(d) &= ~IRQD_ACTIVATED; 382 } 383 384 static inline bool irqd_is_started(struct irq_data *d) 385 { 386 return __irqd_to_state(d) & IRQD_IRQ_STARTED; 387 } 388 389 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) 390 { 391 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; 392 } 393 394 static inline void irqd_set_can_reserve(struct irq_data *d) 395 { 396 __irqd_to_state(d) |= IRQD_CAN_RESERVE; 397 } 398 399 static inline void irqd_clr_can_reserve(struct irq_data *d) 400 { 401 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; 402 } 403 404 static inline bool irqd_can_reserve(struct irq_data *d) 405 { 406 return __irqd_to_state(d) & IRQD_CAN_RESERVE; 407 } 408 409 static inline void irqd_set_msi_nomask_quirk(struct irq_data *d) 410 { 411 __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK; 412 } 413 414 static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d) 415 { 416 __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK; 417 } 418 419 static inline bool irqd_msi_nomask_quirk(struct irq_data *d) 420 { 421 return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK; 422 } 423 424 #undef __irqd_to_state 425 426 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 427 { 428 return d->hwirq; 429 } 430 431 /** 432 * struct irq_chip - hardware interrupt chip descriptor 433 * 434 * @parent_device: pointer to parent device for irqchip 435 * @name: name for /proc/interrupts 436 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 437 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 438 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 439 * @irq_disable: disable the interrupt 440 * @irq_ack: start of a new interrupt 441 * @irq_mask: mask an interrupt source 442 * @irq_mask_ack: ack and mask an interrupt source 443 * @irq_unmask: unmask an interrupt source 444 * @irq_eoi: end of interrupt 445 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force 446 * argument is true, it tells the driver to 447 * unconditionally apply the affinity setting. Sanity 448 * checks against the supplied affinity mask are not 449 * required. This is used for CPU hotplug where the 450 * target CPU is not yet set in the cpu_online_mask. 451 * @irq_retrigger: resend an IRQ to the CPU 452 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 453 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 454 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 455 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 456 * @irq_cpu_online: configure an interrupt source for a secondary CPU 457 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 458 * @irq_suspend: function called from core code on suspend once per 459 * chip, when one or more interrupts are installed 460 * @irq_resume: function called from core code on resume once per chip, 461 * when one ore more interrupts are installed 462 * @irq_pm_shutdown: function called from core code on shutdown once per chip 463 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 464 * @irq_print_chip: optional to print special chip info in show_interrupts 465 * @irq_request_resources: optional to request resources before calling 466 * any other callback related to this irq 467 * @irq_release_resources: optional to release resources acquired with 468 * irq_request_resources 469 * @irq_compose_msi_msg: optional to compose message content for MSI 470 * @irq_write_msi_msg: optional to write message content for MSI 471 * @irq_get_irqchip_state: return the internal state of an interrupt 472 * @irq_set_irqchip_state: set the internal state of a interrupt 473 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 474 * @ipi_send_single: send a single IPI to destination cpus 475 * @ipi_send_mask: send an IPI to destination cpus in cpumask 476 * @irq_nmi_setup: function called from core code before enabling an NMI 477 * @irq_nmi_teardown: function called from core code after disabling an NMI 478 * @flags: chip specific flags 479 */ 480 struct irq_chip { 481 struct device *parent_device; 482 const char *name; 483 unsigned int (*irq_startup)(struct irq_data *data); 484 void (*irq_shutdown)(struct irq_data *data); 485 void (*irq_enable)(struct irq_data *data); 486 void (*irq_disable)(struct irq_data *data); 487 488 void (*irq_ack)(struct irq_data *data); 489 void (*irq_mask)(struct irq_data *data); 490 void (*irq_mask_ack)(struct irq_data *data); 491 void (*irq_unmask)(struct irq_data *data); 492 void (*irq_eoi)(struct irq_data *data); 493 494 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 495 int (*irq_retrigger)(struct irq_data *data); 496 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 497 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 498 499 void (*irq_bus_lock)(struct irq_data *data); 500 void (*irq_bus_sync_unlock)(struct irq_data *data); 501 502 void (*irq_cpu_online)(struct irq_data *data); 503 void (*irq_cpu_offline)(struct irq_data *data); 504 505 void (*irq_suspend)(struct irq_data *data); 506 void (*irq_resume)(struct irq_data *data); 507 void (*irq_pm_shutdown)(struct irq_data *data); 508 509 void (*irq_calc_mask)(struct irq_data *data); 510 511 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 512 int (*irq_request_resources)(struct irq_data *data); 513 void (*irq_release_resources)(struct irq_data *data); 514 515 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 516 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 517 518 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 519 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 520 521 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 522 523 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); 524 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); 525 526 int (*irq_nmi_setup)(struct irq_data *data); 527 void (*irq_nmi_teardown)(struct irq_data *data); 528 529 unsigned long flags; 530 }; 531 532 /* 533 * irq_chip specific flags 534 * 535 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 536 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 537 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 538 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 539 * when irq enabled 540 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 541 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 542 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 543 * IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs 544 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips 545 */ 546 enum { 547 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 548 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 549 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 550 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 551 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 552 IRQCHIP_ONESHOT_SAFE = (1 << 5), 553 IRQCHIP_EOI_THREADED = (1 << 6), 554 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), 555 IRQCHIP_SUPPORTS_NMI = (1 << 8), 556 }; 557 558 #include <linux/irqdesc.h> 559 560 /* 561 * Pick up the arch-dependent methods: 562 */ 563 #include <asm/hw_irq.h> 564 565 #ifndef NR_IRQS_LEGACY 566 # define NR_IRQS_LEGACY 0 567 #endif 568 569 #ifndef ARCH_IRQ_INIT_FLAGS 570 # define ARCH_IRQ_INIT_FLAGS 0 571 #endif 572 573 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 574 575 struct irqaction; 576 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 577 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 578 579 extern void irq_cpu_online(void); 580 extern void irq_cpu_offline(void); 581 extern int irq_set_affinity_locked(struct irq_data *data, 582 const struct cpumask *cpumask, bool force); 583 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 584 585 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) 586 extern void irq_migrate_all_off_this_cpu(void); 587 extern int irq_affinity_online_cpu(unsigned int cpu); 588 #else 589 # define irq_affinity_online_cpu NULL 590 #endif 591 592 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 593 void __irq_move_irq(struct irq_data *data); 594 static inline void irq_move_irq(struct irq_data *data) 595 { 596 if (unlikely(irqd_is_setaffinity_pending(data))) 597 __irq_move_irq(data); 598 } 599 void irq_move_masked_irq(struct irq_data *data); 600 void irq_force_complete_move(struct irq_desc *desc); 601 #else 602 static inline void irq_move_irq(struct irq_data *data) { } 603 static inline void irq_move_masked_irq(struct irq_data *data) { } 604 static inline void irq_force_complete_move(struct irq_desc *desc) { } 605 #endif 606 607 extern int no_irq_affinity; 608 609 #ifdef CONFIG_HARDIRQS_SW_RESEND 610 int irq_set_parent(int irq, int parent_irq); 611 #else 612 static inline int irq_set_parent(int irq, int parent_irq) 613 { 614 return 0; 615 } 616 #endif 617 618 /* 619 * Built-in IRQ handlers for various IRQ types, 620 * callable via desc->handle_irq() 621 */ 622 extern void handle_level_irq(struct irq_desc *desc); 623 extern void handle_fasteoi_irq(struct irq_desc *desc); 624 extern void handle_edge_irq(struct irq_desc *desc); 625 extern void handle_edge_eoi_irq(struct irq_desc *desc); 626 extern void handle_simple_irq(struct irq_desc *desc); 627 extern void handle_untracked_irq(struct irq_desc *desc); 628 extern void handle_percpu_irq(struct irq_desc *desc); 629 extern void handle_percpu_devid_irq(struct irq_desc *desc); 630 extern void handle_bad_irq(struct irq_desc *desc); 631 extern void handle_nested_irq(unsigned int irq); 632 633 extern void handle_fasteoi_nmi(struct irq_desc *desc); 634 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc); 635 636 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 637 extern int irq_chip_pm_get(struct irq_data *data); 638 extern int irq_chip_pm_put(struct irq_data *data); 639 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 640 extern void handle_fasteoi_ack_irq(struct irq_desc *desc); 641 extern void handle_fasteoi_mask_irq(struct irq_desc *desc); 642 extern int irq_chip_set_parent_state(struct irq_data *data, 643 enum irqchip_irq_state which, 644 bool val); 645 extern int irq_chip_get_parent_state(struct irq_data *data, 646 enum irqchip_irq_state which, 647 bool *state); 648 extern void irq_chip_enable_parent(struct irq_data *data); 649 extern void irq_chip_disable_parent(struct irq_data *data); 650 extern void irq_chip_ack_parent(struct irq_data *data); 651 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 652 extern void irq_chip_mask_parent(struct irq_data *data); 653 extern void irq_chip_mask_ack_parent(struct irq_data *data); 654 extern void irq_chip_unmask_parent(struct irq_data *data); 655 extern void irq_chip_eoi_parent(struct irq_data *data); 656 extern int irq_chip_set_affinity_parent(struct irq_data *data, 657 const struct cpumask *dest, 658 bool force); 659 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 660 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 661 void *vcpu_info); 662 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 663 extern int irq_chip_request_resources_parent(struct irq_data *data); 664 extern void irq_chip_release_resources_parent(struct irq_data *data); 665 #endif 666 667 /* Handling of unhandled and spurious interrupts: */ 668 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 669 670 671 /* Enable/disable irq debugging output: */ 672 extern int noirqdebug_setup(char *str); 673 674 /* Checks whether the interrupt can be requested by request_irq(): */ 675 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 676 677 /* Dummy irq-chip implementations: */ 678 extern struct irq_chip no_irq_chip; 679 extern struct irq_chip dummy_irq_chip; 680 681 extern void 682 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 683 irq_flow_handler_t handle, const char *name); 684 685 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 686 irq_flow_handler_t handle) 687 { 688 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 689 } 690 691 extern int irq_set_percpu_devid(unsigned int irq); 692 extern int irq_set_percpu_devid_partition(unsigned int irq, 693 const struct cpumask *affinity); 694 extern int irq_get_percpu_devid_partition(unsigned int irq, 695 struct cpumask *affinity); 696 697 extern void 698 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 699 const char *name); 700 701 static inline void 702 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 703 { 704 __irq_set_handler(irq, handle, 0, NULL); 705 } 706 707 /* 708 * Set a highlevel chained flow handler for a given IRQ. 709 * (a chained handler is automatically enabled and set to 710 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 711 */ 712 static inline void 713 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 714 { 715 __irq_set_handler(irq, handle, 1, NULL); 716 } 717 718 /* 719 * Set a highlevel chained flow handler and its data for a given IRQ. 720 * (a chained handler is automatically enabled and set to 721 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 722 */ 723 void 724 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 725 void *data); 726 727 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 728 729 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 730 { 731 irq_modify_status(irq, 0, set); 732 } 733 734 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 735 { 736 irq_modify_status(irq, clr, 0); 737 } 738 739 static inline void irq_set_noprobe(unsigned int irq) 740 { 741 irq_modify_status(irq, 0, IRQ_NOPROBE); 742 } 743 744 static inline void irq_set_probe(unsigned int irq) 745 { 746 irq_modify_status(irq, IRQ_NOPROBE, 0); 747 } 748 749 static inline void irq_set_nothread(unsigned int irq) 750 { 751 irq_modify_status(irq, 0, IRQ_NOTHREAD); 752 } 753 754 static inline void irq_set_thread(unsigned int irq) 755 { 756 irq_modify_status(irq, IRQ_NOTHREAD, 0); 757 } 758 759 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 760 { 761 if (nest) 762 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 763 else 764 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 765 } 766 767 static inline void irq_set_percpu_devid_flags(unsigned int irq) 768 { 769 irq_set_status_flags(irq, 770 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 771 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 772 } 773 774 /* Set/get chip/data for an IRQ: */ 775 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 776 extern int irq_set_handler_data(unsigned int irq, void *data); 777 extern int irq_set_chip_data(unsigned int irq, void *data); 778 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 779 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 780 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 781 struct msi_desc *entry); 782 extern struct irq_data *irq_get_irq_data(unsigned int irq); 783 784 static inline struct irq_chip *irq_get_chip(unsigned int irq) 785 { 786 struct irq_data *d = irq_get_irq_data(irq); 787 return d ? d->chip : NULL; 788 } 789 790 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 791 { 792 return d->chip; 793 } 794 795 static inline void *irq_get_chip_data(unsigned int irq) 796 { 797 struct irq_data *d = irq_get_irq_data(irq); 798 return d ? d->chip_data : NULL; 799 } 800 801 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 802 { 803 return d->chip_data; 804 } 805 806 static inline void *irq_get_handler_data(unsigned int irq) 807 { 808 struct irq_data *d = irq_get_irq_data(irq); 809 return d ? d->common->handler_data : NULL; 810 } 811 812 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 813 { 814 return d->common->handler_data; 815 } 816 817 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 818 { 819 struct irq_data *d = irq_get_irq_data(irq); 820 return d ? d->common->msi_desc : NULL; 821 } 822 823 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 824 { 825 return d->common->msi_desc; 826 } 827 828 static inline u32 irq_get_trigger_type(unsigned int irq) 829 { 830 struct irq_data *d = irq_get_irq_data(irq); 831 return d ? irqd_get_trigger_type(d) : 0; 832 } 833 834 static inline int irq_common_data_get_node(struct irq_common_data *d) 835 { 836 #ifdef CONFIG_NUMA 837 return d->node; 838 #else 839 return 0; 840 #endif 841 } 842 843 static inline int irq_data_get_node(struct irq_data *d) 844 { 845 return irq_common_data_get_node(d->common); 846 } 847 848 static inline struct cpumask *irq_get_affinity_mask(int irq) 849 { 850 struct irq_data *d = irq_get_irq_data(irq); 851 852 return d ? d->common->affinity : NULL; 853 } 854 855 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 856 { 857 return d->common->affinity; 858 } 859 860 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 861 static inline 862 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 863 { 864 return d->common->effective_affinity; 865 } 866 static inline void irq_data_update_effective_affinity(struct irq_data *d, 867 const struct cpumask *m) 868 { 869 cpumask_copy(d->common->effective_affinity, m); 870 } 871 #else 872 static inline void irq_data_update_effective_affinity(struct irq_data *d, 873 const struct cpumask *m) 874 { 875 } 876 static inline 877 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 878 { 879 return d->common->affinity; 880 } 881 #endif 882 883 unsigned int arch_dynirq_lower_bound(unsigned int from); 884 885 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 886 struct module *owner, 887 const struct irq_affinity_desc *affinity); 888 889 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, 890 unsigned int cnt, int node, struct module *owner, 891 const struct irq_affinity_desc *affinity); 892 893 /* use macros to avoid needing export.h for THIS_MODULE */ 894 #define irq_alloc_descs(irq, from, cnt, node) \ 895 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) 896 897 #define irq_alloc_desc(node) \ 898 irq_alloc_descs(-1, 0, 1, node) 899 900 #define irq_alloc_desc_at(at, node) \ 901 irq_alloc_descs(at, at, 1, node) 902 903 #define irq_alloc_desc_from(from, node) \ 904 irq_alloc_descs(-1, from, 1, node) 905 906 #define irq_alloc_descs_from(from, cnt, node) \ 907 irq_alloc_descs(-1, from, cnt, node) 908 909 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ 910 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) 911 912 #define devm_irq_alloc_desc(dev, node) \ 913 devm_irq_alloc_descs(dev, -1, 0, 1, node) 914 915 #define devm_irq_alloc_desc_at(dev, at, node) \ 916 devm_irq_alloc_descs(dev, at, at, 1, node) 917 918 #define devm_irq_alloc_desc_from(dev, from, node) \ 919 devm_irq_alloc_descs(dev, -1, from, 1, node) 920 921 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ 922 devm_irq_alloc_descs(dev, -1, from, cnt, node) 923 924 void irq_free_descs(unsigned int irq, unsigned int cnt); 925 static inline void irq_free_desc(unsigned int irq) 926 { 927 irq_free_descs(irq, 1); 928 } 929 930 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 931 unsigned int irq_alloc_hwirqs(int cnt, int node); 932 static inline unsigned int irq_alloc_hwirq(int node) 933 { 934 return irq_alloc_hwirqs(1, node); 935 } 936 void irq_free_hwirqs(unsigned int from, int cnt); 937 static inline void irq_free_hwirq(unsigned int irq) 938 { 939 return irq_free_hwirqs(irq, 1); 940 } 941 int arch_setup_hwirq(unsigned int irq, int node); 942 void arch_teardown_hwirq(unsigned int irq); 943 #endif 944 945 #ifdef CONFIG_GENERIC_IRQ_LEGACY 946 void irq_init_desc(unsigned int irq); 947 #endif 948 949 /** 950 * struct irq_chip_regs - register offsets for struct irq_gci 951 * @enable: Enable register offset to reg_base 952 * @disable: Disable register offset to reg_base 953 * @mask: Mask register offset to reg_base 954 * @ack: Ack register offset to reg_base 955 * @eoi: Eoi register offset to reg_base 956 * @type: Type configuration register offset to reg_base 957 * @polarity: Polarity configuration register offset to reg_base 958 */ 959 struct irq_chip_regs { 960 unsigned long enable; 961 unsigned long disable; 962 unsigned long mask; 963 unsigned long ack; 964 unsigned long eoi; 965 unsigned long type; 966 unsigned long polarity; 967 }; 968 969 /** 970 * struct irq_chip_type - Generic interrupt chip instance for a flow type 971 * @chip: The real interrupt chip which provides the callbacks 972 * @regs: Register offsets for this chip 973 * @handler: Flow handler associated with this chip 974 * @type: Chip can handle these flow types 975 * @mask_cache_priv: Cached mask register private to the chip type 976 * @mask_cache: Pointer to cached mask register 977 * 978 * A irq_generic_chip can have several instances of irq_chip_type when 979 * it requires different functions and register offsets for different 980 * flow types. 981 */ 982 struct irq_chip_type { 983 struct irq_chip chip; 984 struct irq_chip_regs regs; 985 irq_flow_handler_t handler; 986 u32 type; 987 u32 mask_cache_priv; 988 u32 *mask_cache; 989 }; 990 991 /** 992 * struct irq_chip_generic - Generic irq chip data structure 993 * @lock: Lock to protect register and cache data access 994 * @reg_base: Register base address (virtual) 995 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 996 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 997 * @suspend: Function called from core code on suspend once per 998 * chip; can be useful instead of irq_chip::suspend to 999 * handle chip details even when no interrupts are in use 1000 * @resume: Function called from core code on resume once per chip; 1001 * can be useful instead of irq_chip::suspend to handle 1002 * chip details even when no interrupts are in use 1003 * @irq_base: Interrupt base nr for this chip 1004 * @irq_cnt: Number of interrupts handled by this chip 1005 * @mask_cache: Cached mask register shared between all chip types 1006 * @type_cache: Cached type register 1007 * @polarity_cache: Cached polarity register 1008 * @wake_enabled: Interrupt can wakeup from suspend 1009 * @wake_active: Interrupt is marked as an wakeup from suspend source 1010 * @num_ct: Number of available irq_chip_type instances (usually 1) 1011 * @private: Private data for non generic chip callbacks 1012 * @installed: bitfield to denote installed interrupts 1013 * @unused: bitfield to denote unused interrupts 1014 * @domain: irq domain pointer 1015 * @list: List head for keeping track of instances 1016 * @chip_types: Array of interrupt irq_chip_types 1017 * 1018 * Note, that irq_chip_generic can have multiple irq_chip_type 1019 * implementations which can be associated to a particular irq line of 1020 * an irq_chip_generic instance. That allows to share and protect 1021 * state in an irq_chip_generic instance when we need to implement 1022 * different flow mechanisms (level/edge) for it. 1023 */ 1024 struct irq_chip_generic { 1025 raw_spinlock_t lock; 1026 void __iomem *reg_base; 1027 u32 (*reg_readl)(void __iomem *addr); 1028 void (*reg_writel)(u32 val, void __iomem *addr); 1029 void (*suspend)(struct irq_chip_generic *gc); 1030 void (*resume)(struct irq_chip_generic *gc); 1031 unsigned int irq_base; 1032 unsigned int irq_cnt; 1033 u32 mask_cache; 1034 u32 type_cache; 1035 u32 polarity_cache; 1036 u32 wake_enabled; 1037 u32 wake_active; 1038 unsigned int num_ct; 1039 void *private; 1040 unsigned long installed; 1041 unsigned long unused; 1042 struct irq_domain *domain; 1043 struct list_head list; 1044 struct irq_chip_type chip_types[]; 1045 }; 1046 1047 /** 1048 * enum irq_gc_flags - Initialization flags for generic irq chips 1049 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 1050 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 1051 * irq chips which need to call irq_set_wake() on 1052 * the parent irq. Usually GPIO implementations 1053 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 1054 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 1055 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 1056 */ 1057 enum irq_gc_flags { 1058 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 1059 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 1060 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 1061 IRQ_GC_NO_MASK = 1 << 3, 1062 IRQ_GC_BE_IO = 1 << 4, 1063 }; 1064 1065 /* 1066 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 1067 * @irqs_per_chip: Number of interrupts per chip 1068 * @num_chips: Number of chips 1069 * @irq_flags_to_set: IRQ* flags to set on irq setup 1070 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 1071 * @gc_flags: Generic chip specific setup flags 1072 * @gc: Array of pointers to generic interrupt chips 1073 */ 1074 struct irq_domain_chip_generic { 1075 unsigned int irqs_per_chip; 1076 unsigned int num_chips; 1077 unsigned int irq_flags_to_clear; 1078 unsigned int irq_flags_to_set; 1079 enum irq_gc_flags gc_flags; 1080 struct irq_chip_generic *gc[]; 1081 }; 1082 1083 /* Generic chip callback functions */ 1084 void irq_gc_noop(struct irq_data *d); 1085 void irq_gc_mask_disable_reg(struct irq_data *d); 1086 void irq_gc_mask_set_bit(struct irq_data *d); 1087 void irq_gc_mask_clr_bit(struct irq_data *d); 1088 void irq_gc_unmask_enable_reg(struct irq_data *d); 1089 void irq_gc_ack_set_bit(struct irq_data *d); 1090 void irq_gc_ack_clr_bit(struct irq_data *d); 1091 void irq_gc_mask_disable_and_ack_set(struct irq_data *d); 1092 void irq_gc_eoi(struct irq_data *d); 1093 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 1094 1095 /* Setup functions for irq_chip_generic */ 1096 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 1097 irq_hw_number_t hw_irq); 1098 struct irq_chip_generic * 1099 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 1100 void __iomem *reg_base, irq_flow_handler_t handler); 1101 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 1102 enum irq_gc_flags flags, unsigned int clr, 1103 unsigned int set); 1104 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 1105 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 1106 unsigned int clr, unsigned int set); 1107 1108 struct irq_chip_generic * 1109 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, 1110 unsigned int irq_base, void __iomem *reg_base, 1111 irq_flow_handler_t handler); 1112 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, 1113 u32 msk, enum irq_gc_flags flags, 1114 unsigned int clr, unsigned int set); 1115 1116 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 1117 1118 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 1119 int num_ct, const char *name, 1120 irq_flow_handler_t handler, 1121 unsigned int clr, unsigned int set, 1122 enum irq_gc_flags flags); 1123 1124 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ 1125 handler, clr, set, flags) \ 1126 ({ \ 1127 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ 1128 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ 1129 handler, clr, set, flags); \ 1130 }) 1131 1132 static inline void irq_free_generic_chip(struct irq_chip_generic *gc) 1133 { 1134 kfree(gc); 1135 } 1136 1137 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, 1138 u32 msk, unsigned int clr, 1139 unsigned int set) 1140 { 1141 irq_remove_generic_chip(gc, msk, clr, set); 1142 irq_free_generic_chip(gc); 1143 } 1144 1145 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 1146 { 1147 return container_of(d->chip, struct irq_chip_type, chip); 1148 } 1149 1150 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 1151 1152 #ifdef CONFIG_SMP 1153 static inline void irq_gc_lock(struct irq_chip_generic *gc) 1154 { 1155 raw_spin_lock(&gc->lock); 1156 } 1157 1158 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 1159 { 1160 raw_spin_unlock(&gc->lock); 1161 } 1162 #else 1163 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 1164 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 1165 #endif 1166 1167 /* 1168 * The irqsave variants are for usage in non interrupt code. Do not use 1169 * them in irq_chip callbacks. Use irq_gc_lock() instead. 1170 */ 1171 #define irq_gc_lock_irqsave(gc, flags) \ 1172 raw_spin_lock_irqsave(&(gc)->lock, flags) 1173 1174 #define irq_gc_unlock_irqrestore(gc, flags) \ 1175 raw_spin_unlock_irqrestore(&(gc)->lock, flags) 1176 1177 static inline void irq_reg_writel(struct irq_chip_generic *gc, 1178 u32 val, int reg_offset) 1179 { 1180 if (gc->reg_writel) 1181 gc->reg_writel(val, gc->reg_base + reg_offset); 1182 else 1183 writel(val, gc->reg_base + reg_offset); 1184 } 1185 1186 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 1187 int reg_offset) 1188 { 1189 if (gc->reg_readl) 1190 return gc->reg_readl(gc->reg_base + reg_offset); 1191 else 1192 return readl(gc->reg_base + reg_offset); 1193 } 1194 1195 struct irq_matrix; 1196 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, 1197 unsigned int alloc_start, 1198 unsigned int alloc_end); 1199 void irq_matrix_online(struct irq_matrix *m); 1200 void irq_matrix_offline(struct irq_matrix *m); 1201 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); 1202 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); 1203 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); 1204 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk, 1205 unsigned int *mapped_cpu); 1206 void irq_matrix_reserve(struct irq_matrix *m); 1207 void irq_matrix_remove_reserved(struct irq_matrix *m); 1208 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, 1209 bool reserved, unsigned int *mapped_cpu); 1210 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, 1211 unsigned int bit, bool managed); 1212 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); 1213 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); 1214 unsigned int irq_matrix_allocated(struct irq_matrix *m); 1215 unsigned int irq_matrix_reserved(struct irq_matrix *m); 1216 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); 1217 1218 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ 1219 #define INVALID_HWIRQ (~0UL) 1220 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); 1221 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); 1222 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); 1223 int ipi_send_single(unsigned int virq, unsigned int cpu); 1224 int ipi_send_mask(unsigned int virq, const struct cpumask *dest); 1225 1226 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 1227 /* 1228 * Registers a generic IRQ handling function as the top-level IRQ handler in 1229 * the system, which is generally the first C code called from an assembly 1230 * architecture-specific interrupt handler. 1231 * 1232 * Returns 0 on success, or -EBUSY if an IRQ handler has already been 1233 * registered. 1234 */ 1235 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); 1236 1237 /* 1238 * Allows interrupt handlers to find the irqchip that's been registered as the 1239 * top-level IRQ handler. 1240 */ 1241 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; 1242 #endif 1243 1244 #endif /* _LINUX_IRQ_H */ 1245