1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Support code for Analog Devices Sigma-Delta ADCs 4 * 5 * Copyright 2012 Analog Devices Inc. 6 * Author: Lars-Peter Clausen <lars@metafoo.de> 7 */ 8 #ifndef __AD_SIGMA_DELTA_H__ 9 #define __AD_SIGMA_DELTA_H__ 10 11 enum ad_sigma_delta_mode { 12 AD_SD_MODE_CONTINUOUS = 0, 13 AD_SD_MODE_SINGLE = 1, 14 AD_SD_MODE_IDLE = 2, 15 AD_SD_MODE_POWERDOWN = 3, 16 }; 17 18 /** 19 * struct ad_sigma_delta_calib_data - Calibration data for Sigma Delta devices 20 * @mode: Calibration mode. 21 * @channel: Calibration channel. 22 */ 23 struct ad_sd_calib_data { 24 unsigned int mode; 25 unsigned int channel; 26 }; 27 28 struct ad_sigma_delta; 29 struct device; 30 struct iio_dev; 31 32 /** 33 * struct ad_sigma_delta_info - Sigma Delta driver specific callbacks and options 34 * @set_channel: Will be called to select the current channel, may be NULL. 35 * @append_status: Will be called to enable status append at the end of the sample, may be NULL. 36 * @set_mode: Will be called to select the current mode, may be NULL. 37 * @disable_all: Will be called to disable all channels, may be NULL. 38 * @postprocess_sample: Is called for each sampled data word, can be used to 39 * modify or drop the sample data, it, may be NULL. 40 * @has_registers: true if the device has writable and readable registers, false 41 * if there is just one read-only sample data shift register. 42 * @addr_shift: Shift of the register address in the communications register. 43 * @read_mask: Mask for the communications register having the read bit set. 44 * @status_ch_mask: Mask for the channel number stored in status register. 45 * @data_reg: Address of the data register, if 0 the default address of 0x3 will 46 * be used. 47 * @irq_flags: flags for the interrupt used by the triggered buffer 48 * @num_slots: Number of sequencer slots 49 */ 50 struct ad_sigma_delta_info { 51 int (*set_channel)(struct ad_sigma_delta *, unsigned int channel); 52 int (*append_status)(struct ad_sigma_delta *, bool append); 53 int (*set_mode)(struct ad_sigma_delta *, enum ad_sigma_delta_mode mode); 54 int (*disable_all)(struct ad_sigma_delta *); 55 int (*postprocess_sample)(struct ad_sigma_delta *, unsigned int raw_sample); 56 bool has_registers; 57 unsigned int addr_shift; 58 unsigned int read_mask; 59 unsigned int status_ch_mask; 60 unsigned int data_reg; 61 unsigned long irq_flags; 62 unsigned int num_slots; 63 }; 64 65 /** 66 * struct ad_sigma_delta - Sigma Delta device struct 67 * @spi: The spi device associated with the Sigma Delta device. 68 * @trig: The IIO trigger associated with the Sigma Delta device. 69 * 70 * Most of the fields are private to the sigma delta library code and should not 71 * be accessed by individual drivers. 72 */ 73 struct ad_sigma_delta { 74 struct spi_device *spi; 75 struct iio_trigger *trig; 76 77 /* private: */ 78 struct completion completion; 79 bool irq_dis; 80 81 bool bus_locked; 82 bool keep_cs_asserted; 83 84 uint8_t comm; 85 86 const struct ad_sigma_delta_info *info; 87 unsigned int active_slots; 88 unsigned int current_slot; 89 unsigned int num_slots; 90 bool status_appended; 91 /* map slots to channels in order to know what to expect from devices */ 92 unsigned int *slots; 93 uint8_t *samples_buf; 94 95 /* 96 * DMA (thus cache coherency maintenance) requires the 97 * transfer buffers to live in their own cache lines. 98 * 'tx_buf' is up to 32 bits. 99 * 'rx_buf' is up to 32 bits per sample + 64 bit timestamp, 100 * rounded to 16 bytes to take into account padding. 101 */ 102 uint8_t tx_buf[4] ____cacheline_aligned; 103 uint8_t rx_buf[16] __aligned(8); 104 }; 105 106 static inline int ad_sigma_delta_set_channel(struct ad_sigma_delta *sd, 107 unsigned int channel) 108 { 109 if (sd->info->set_channel) 110 return sd->info->set_channel(sd, channel); 111 112 return 0; 113 } 114 115 static inline int ad_sigma_delta_append_status(struct ad_sigma_delta *sd, bool append) 116 { 117 int ret; 118 119 if (sd->info->append_status) { 120 ret = sd->info->append_status(sd, append); 121 if (ret < 0) 122 return ret; 123 124 sd->status_appended = append; 125 } 126 127 return 0; 128 } 129 130 static inline int ad_sigma_delta_disable_all(struct ad_sigma_delta *sd) 131 { 132 if (sd->info->disable_all) 133 return sd->info->disable_all(sd); 134 135 return 0; 136 } 137 138 static inline int ad_sigma_delta_set_mode(struct ad_sigma_delta *sd, 139 unsigned int mode) 140 { 141 if (sd->info->set_mode) 142 return sd->info->set_mode(sd, mode); 143 144 return 0; 145 } 146 147 static inline int ad_sigma_delta_postprocess_sample(struct ad_sigma_delta *sd, 148 unsigned int raw_sample) 149 { 150 if (sd->info->postprocess_sample) 151 return sd->info->postprocess_sample(sd, raw_sample); 152 153 return 0; 154 } 155 156 void ad_sd_set_comm(struct ad_sigma_delta *sigma_delta, uint8_t comm); 157 int ad_sd_write_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg, 158 unsigned int size, unsigned int val); 159 int ad_sd_read_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg, 160 unsigned int size, unsigned int *val); 161 162 int ad_sd_reset(struct ad_sigma_delta *sigma_delta, 163 unsigned int reset_length); 164 165 int ad_sigma_delta_single_conversion(struct iio_dev *indio_dev, 166 const struct iio_chan_spec *chan, int *val); 167 int ad_sd_calibrate(struct ad_sigma_delta *sigma_delta, 168 unsigned int mode, unsigned int channel); 169 int ad_sd_calibrate_all(struct ad_sigma_delta *sigma_delta, 170 const struct ad_sd_calib_data *cd, unsigned int n); 171 int ad_sd_init(struct ad_sigma_delta *sigma_delta, struct iio_dev *indio_dev, 172 struct spi_device *spi, const struct ad_sigma_delta_info *info); 173 174 int devm_ad_sd_setup_buffer_and_trigger(struct device *dev, struct iio_dev *indio_dev); 175 176 int ad_sd_validate_trigger(struct iio_dev *indio_dev, struct iio_trigger *trig); 177 178 #endif 179