1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_GPIO_DRIVER_H 3 #define __LINUX_GPIO_DRIVER_H 4 5 #include <linux/device.h> 6 #include <linux/types.h> 7 #include <linux/irq.h> 8 #include <linux/irqchip/chained_irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/lockdep.h> 11 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 14 struct gpio_desc; 15 struct of_phandle_args; 16 struct device_node; 17 struct seq_file; 18 struct gpio_device; 19 struct module; 20 enum gpiod_flags; 21 enum gpio_lookup_flags; 22 23 struct gpio_chip; 24 25 #define GPIO_LINE_DIRECTION_IN 1 26 #define GPIO_LINE_DIRECTION_OUT 0 27 28 /** 29 * struct gpio_irq_chip - GPIO interrupt controller 30 */ 31 struct gpio_irq_chip { 32 /** 33 * @chip: 34 * 35 * GPIO IRQ chip implementation, provided by GPIO driver. 36 */ 37 struct irq_chip *chip; 38 39 /** 40 * @domain: 41 * 42 * Interrupt translation domain; responsible for mapping between GPIO 43 * hwirq number and Linux IRQ number. 44 */ 45 struct irq_domain *domain; 46 47 /** 48 * @domain_ops: 49 * 50 * Table of interrupt domain operations for this IRQ chip. 51 */ 52 const struct irq_domain_ops *domain_ops; 53 54 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 55 /** 56 * @fwnode: 57 * 58 * Firmware node corresponding to this gpiochip/irqchip, necessary 59 * for hierarchical irqdomain support. 60 */ 61 struct fwnode_handle *fwnode; 62 63 /** 64 * @parent_domain: 65 * 66 * If non-NULL, will be set as the parent of this GPIO interrupt 67 * controller's IRQ domain to establish a hierarchical interrupt 68 * domain. The presence of this will activate the hierarchical 69 * interrupt support. 70 */ 71 struct irq_domain *parent_domain; 72 73 /** 74 * @child_to_parent_hwirq: 75 * 76 * This callback translates a child hardware IRQ offset to a parent 77 * hardware IRQ offset on a hierarchical interrupt chip. The child 78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the 79 * ngpio field of struct gpio_chip) and the corresponding parent 80 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by 81 * the driver. The driver can calculate this from an offset or using 82 * a lookup table or whatever method is best for this chip. Return 83 * 0 on successful translation in the driver. 84 * 85 * If some ranges of hardware IRQs do not have a corresponding parent 86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and 87 * @need_valid_mask to make these GPIO lines unavailable for 88 * translation. 89 */ 90 int (*child_to_parent_hwirq)(struct gpio_chip *chip, 91 unsigned int child_hwirq, 92 unsigned int child_type, 93 unsigned int *parent_hwirq, 94 unsigned int *parent_type); 95 96 /** 97 * @populate_parent_alloc_arg : 98 * 99 * This optional callback allocates and populates the specific struct 100 * for the parent's IRQ domain. If this is not specified, then 101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell 102 * variant named &gpiochip_populate_parent_fwspec_fourcell is also 103 * available. 104 */ 105 void *(*populate_parent_alloc_arg)(struct gpio_chip *chip, 106 unsigned int parent_hwirq, 107 unsigned int parent_type); 108 109 /** 110 * @child_offset_to_irq: 111 * 112 * This optional callback is used to translate the child's GPIO line 113 * offset on the GPIO chip to an IRQ number for the GPIO to_irq() 114 * callback. If this is not specified, then a default callback will be 115 * provided that returns the line offset. 116 */ 117 unsigned int (*child_offset_to_irq)(struct gpio_chip *chip, 118 unsigned int pin); 119 120 /** 121 * @child_irq_domain_ops: 122 * 123 * The IRQ domain operations that will be used for this GPIO IRQ 124 * chip. If no operations are provided, then default callbacks will 125 * be populated to setup the IRQ hierarchy. Some drivers need to 126 * supply their own translate function. 127 */ 128 struct irq_domain_ops child_irq_domain_ops; 129 #endif 130 131 /** 132 * @handler: 133 * 134 * The IRQ handler to use (often a predefined IRQ core function) for 135 * GPIO IRQs, provided by GPIO driver. 136 */ 137 irq_flow_handler_t handler; 138 139 /** 140 * @default_type: 141 * 142 * Default IRQ triggering type applied during GPIO driver 143 * initialization, provided by GPIO driver. 144 */ 145 unsigned int default_type; 146 147 /** 148 * @lock_key: 149 * 150 * Per GPIO IRQ chip lockdep class for IRQ lock. 151 */ 152 struct lock_class_key *lock_key; 153 154 /** 155 * @request_key: 156 * 157 * Per GPIO IRQ chip lockdep class for IRQ request. 158 */ 159 struct lock_class_key *request_key; 160 161 /** 162 * @parent_handler: 163 * 164 * The interrupt handler for the GPIO chip's parent interrupts, may be 165 * NULL if the parent interrupts are nested rather than cascaded. 166 */ 167 irq_flow_handler_t parent_handler; 168 169 /** 170 * @parent_handler_data: 171 * 172 * Data associated, and passed to, the handler for the parent 173 * interrupt. 174 */ 175 void *parent_handler_data; 176 177 /** 178 * @num_parents: 179 * 180 * The number of interrupt parents of a GPIO chip. 181 */ 182 unsigned int num_parents; 183 184 /** 185 * @parents: 186 * 187 * A list of interrupt parents of a GPIO chip. This is owned by the 188 * driver, so the core will only reference this list, not modify it. 189 */ 190 unsigned int *parents; 191 192 /** 193 * @map: 194 * 195 * A list of interrupt parents for each line of a GPIO chip. 196 */ 197 unsigned int *map; 198 199 /** 200 * @threaded: 201 * 202 * True if set the interrupt handling uses nested threads. 203 */ 204 bool threaded; 205 206 /** 207 * @init_hw: optional routine to initialize hardware before 208 * an IRQ chip will be added. This is quite useful when 209 * a particular driver wants to clear IRQ related registers 210 * in order to avoid undesired events. 211 */ 212 int (*init_hw)(struct gpio_chip *chip); 213 214 /** 215 * @init_valid_mask: optional routine to initialize @valid_mask, to be 216 * used if not all GPIO lines are valid interrupts. Sometimes some 217 * lines just cannot fire interrupts, and this routine, when defined, 218 * is passed a bitmap in "valid_mask" and it will have ngpios 219 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can 220 * then directly set some bits to "0" if they cannot be used for 221 * interrupts. 222 */ 223 void (*init_valid_mask)(struct gpio_chip *chip, 224 unsigned long *valid_mask, 225 unsigned int ngpios); 226 227 /** 228 * @valid_mask: 229 * 230 * If not %NULL holds bitmask of GPIOs which are valid to be included 231 * in IRQ domain of the chip. 232 */ 233 unsigned long *valid_mask; 234 235 /** 236 * @first: 237 * 238 * Required for static IRQ allocation. If set, irq_domain_add_simple() 239 * will allocate and map all IRQs during initialization. 240 */ 241 unsigned int first; 242 243 /** 244 * @irq_enable: 245 * 246 * Store old irq_chip irq_enable callback 247 */ 248 void (*irq_enable)(struct irq_data *data); 249 250 /** 251 * @irq_disable: 252 * 253 * Store old irq_chip irq_disable callback 254 */ 255 void (*irq_disable)(struct irq_data *data); 256 }; 257 258 /** 259 * struct gpio_chip - abstract a GPIO controller 260 * @label: a functional name for the GPIO device, such as a part 261 * number or the name of the SoC IP-block implementing it. 262 * @gpiodev: the internal state holder, opaque struct 263 * @parent: optional parent device providing the GPIOs 264 * @owner: helps prevent removal of modules exporting active GPIOs 265 * @request: optional hook for chip-specific activation, such as 266 * enabling module power and clock; may sleep 267 * @free: optional hook for chip-specific deactivation, such as 268 * disabling module power and clock; may sleep 269 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 270 * (same as GPIOF_DIR_XXX), or negative error. 271 * It is recommended to always implement this function, even on 272 * input-only or output-only gpio chips. 273 * @direction_input: configures signal "offset" as input, or returns error 274 * This can be omitted on input-only or output-only gpio chips. 275 * @direction_output: configures signal "offset" as output, or returns error 276 * This can be omitted on input-only or output-only gpio chips. 277 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 278 * @get_multiple: reads values for multiple signals defined by "mask" and 279 * stores them in "bits", returns 0 on success or negative error 280 * @set: assigns output value for signal "offset" 281 * @set_multiple: assigns output values for multiple signals defined by "mask" 282 * @set_config: optional hook for all kinds of settings. Uses the same 283 * packed config format as generic pinconf. 284 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings; 285 * implementation may not sleep 286 * @dbg_show: optional routine to show contents in debugfs; default code 287 * will be used when this is omitted, but custom code can show extra 288 * state (such as pullup/pulldown configuration). 289 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if 290 * not all GPIOs are valid. 291 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when 292 * requires special mapping of the pins that provides GPIO functionality. 293 * It is called after adding GPIO chip and before adding IRQ chip. 294 * @base: identifies the first GPIO number handled by this chip; 295 * or, if negative during registration, requests dynamic ID allocation. 296 * DEPRECATION: providing anything non-negative and nailing the base 297 * offset of GPIO chips is deprecated. Please pass -1 as base to 298 * let gpiolib select the chip base in all possible cases. We want to 299 * get rid of the static GPIO number space in the long run. 300 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 301 * handled is (base + ngpio - 1). 302 * @names: if set, must be an array of strings to use as alternative 303 * names for the GPIOs in this chip. Any entry in the array 304 * may be NULL if there is no alias for the GPIO, however the 305 * array must be @ngpio entries long. A name can include a single printk 306 * format specifier for an unsigned int. It is substituted by the actual 307 * number of the gpio. 308 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 309 * must while accessing GPIO expander chips over I2C or SPI. This 310 * implies that if the chip supports IRQs, these IRQs need to be threaded 311 * as the chip access may sleep when e.g. reading out the IRQ status 312 * registers. 313 * @read_reg: reader function for generic GPIO 314 * @write_reg: writer function for generic GPIO 315 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing 316 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the 317 * generic GPIO core. It is for internal housekeeping only. 318 * @reg_dat: data (in) register for generic GPIO 319 * @reg_set: output set register (out=high) for generic GPIO 320 * @reg_clr: output clear register (out=low) for generic GPIO 321 * @reg_dir_out: direction out setting register for generic GPIO 322 * @reg_dir_in: direction in setting register for generic GPIO 323 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 324 * be read and we need to rely on out internal state tracking. 325 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 326 * <register width> * 8 327 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 328 * shadowed and real data registers writes together. 329 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 330 * safely. 331 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 332 * direction safely. A "1" in this word means the line is set as 333 * output. 334 * 335 * A gpio_chip can help platforms abstract various sources of GPIOs so 336 * they can all be accessed through a common programing interface. 337 * Example sources would be SOC controllers, FPGAs, multifunction 338 * chips, dedicated GPIO expanders, and so on. 339 * 340 * Each chip controls a number of signals, identified in method calls 341 * by "offset" values in the range 0..(@ngpio - 1). When those signals 342 * are referenced through calls like gpio_get_value(gpio), the offset 343 * is calculated by subtracting @base from the gpio number. 344 */ 345 struct gpio_chip { 346 const char *label; 347 struct gpio_device *gpiodev; 348 struct device *parent; 349 struct module *owner; 350 351 int (*request)(struct gpio_chip *chip, 352 unsigned offset); 353 void (*free)(struct gpio_chip *chip, 354 unsigned offset); 355 int (*get_direction)(struct gpio_chip *chip, 356 unsigned offset); 357 int (*direction_input)(struct gpio_chip *chip, 358 unsigned offset); 359 int (*direction_output)(struct gpio_chip *chip, 360 unsigned offset, int value); 361 int (*get)(struct gpio_chip *chip, 362 unsigned offset); 363 int (*get_multiple)(struct gpio_chip *chip, 364 unsigned long *mask, 365 unsigned long *bits); 366 void (*set)(struct gpio_chip *chip, 367 unsigned offset, int value); 368 void (*set_multiple)(struct gpio_chip *chip, 369 unsigned long *mask, 370 unsigned long *bits); 371 int (*set_config)(struct gpio_chip *chip, 372 unsigned offset, 373 unsigned long config); 374 int (*to_irq)(struct gpio_chip *chip, 375 unsigned offset); 376 377 void (*dbg_show)(struct seq_file *s, 378 struct gpio_chip *chip); 379 380 int (*init_valid_mask)(struct gpio_chip *chip, 381 unsigned long *valid_mask, 382 unsigned int ngpios); 383 384 int (*add_pin_ranges)(struct gpio_chip *chip); 385 386 int base; 387 u16 ngpio; 388 const char *const *names; 389 bool can_sleep; 390 391 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 392 unsigned long (*read_reg)(void __iomem *reg); 393 void (*write_reg)(void __iomem *reg, unsigned long data); 394 bool be_bits; 395 void __iomem *reg_dat; 396 void __iomem *reg_set; 397 void __iomem *reg_clr; 398 void __iomem *reg_dir_out; 399 void __iomem *reg_dir_in; 400 bool bgpio_dir_unreadable; 401 int bgpio_bits; 402 spinlock_t bgpio_lock; 403 unsigned long bgpio_data; 404 unsigned long bgpio_dir; 405 #endif /* CONFIG_GPIO_GENERIC */ 406 407 #ifdef CONFIG_GPIOLIB_IRQCHIP 408 /* 409 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 410 * to handle IRQs for most practical cases. 411 */ 412 413 /** 414 * @irq: 415 * 416 * Integrates interrupt chip functionality with the GPIO chip. Can be 417 * used to handle IRQs for most practical cases. 418 */ 419 struct gpio_irq_chip irq; 420 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 421 422 /** 423 * @valid_mask: 424 * 425 * If not %NULL holds bitmask of GPIOs which are valid to be used 426 * from the chip. 427 */ 428 unsigned long *valid_mask; 429 430 #if defined(CONFIG_OF_GPIO) 431 /* 432 * If CONFIG_OF is enabled, then all GPIO controllers described in the 433 * device tree automatically may have an OF translation 434 */ 435 436 /** 437 * @of_node: 438 * 439 * Pointer to a device tree node representing this GPIO controller. 440 */ 441 struct device_node *of_node; 442 443 /** 444 * @of_gpio_n_cells: 445 * 446 * Number of cells used to form the GPIO specifier. 447 */ 448 unsigned int of_gpio_n_cells; 449 450 /** 451 * @of_xlate: 452 * 453 * Callback to translate a device tree GPIO specifier into a chip- 454 * relative GPIO number and flags. 455 */ 456 int (*of_xlate)(struct gpio_chip *gc, 457 const struct of_phandle_args *gpiospec, u32 *flags); 458 #endif /* CONFIG_OF_GPIO */ 459 }; 460 461 extern const char *gpiochip_is_requested(struct gpio_chip *chip, 462 unsigned offset); 463 464 /* add/remove chips */ 465 extern int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data, 466 struct lock_class_key *lock_key, 467 struct lock_class_key *request_key); 468 469 /** 470 * gpiochip_add_data() - register a gpio_chip 471 * @chip: the chip to register, with chip->base initialized 472 * @data: driver-private data associated with this chip 473 * 474 * Context: potentially before irqs will work 475 * 476 * When gpiochip_add_data() is called very early during boot, so that GPIOs 477 * can be freely used, the chip->parent device must be registered before 478 * the gpio framework's arch_initcall(). Otherwise sysfs initialization 479 * for GPIOs will fail rudely. 480 * 481 * gpiochip_add_data() must only be called after gpiolib initialization, 482 * ie after core_initcall(). 483 * 484 * If chip->base is negative, this requests dynamic assignment of 485 * a range of valid GPIOs. 486 * 487 * Returns: 488 * A negative errno if the chip can't be registered, such as because the 489 * chip->base is invalid or already associated with a different chip. 490 * Otherwise it returns zero as a success code. 491 */ 492 #ifdef CONFIG_LOCKDEP 493 #define gpiochip_add_data(chip, data) ({ \ 494 static struct lock_class_key lock_key; \ 495 static struct lock_class_key request_key; \ 496 gpiochip_add_data_with_key(chip, data, &lock_key, \ 497 &request_key); \ 498 }) 499 #else 500 #define gpiochip_add_data(chip, data) gpiochip_add_data_with_key(chip, data, NULL, NULL) 501 #endif /* CONFIG_LOCKDEP */ 502 503 static inline int gpiochip_add(struct gpio_chip *chip) 504 { 505 return gpiochip_add_data(chip, NULL); 506 } 507 extern void gpiochip_remove(struct gpio_chip *chip); 508 extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip, 509 void *data); 510 511 extern struct gpio_chip *gpiochip_find(void *data, 512 int (*match)(struct gpio_chip *chip, void *data)); 513 514 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset); 515 int gpiochip_reqres_irq(struct gpio_chip *chip, unsigned int offset); 516 void gpiochip_relres_irq(struct gpio_chip *chip, unsigned int offset); 517 void gpiochip_disable_irq(struct gpio_chip *chip, unsigned int offset); 518 void gpiochip_enable_irq(struct gpio_chip *chip, unsigned int offset); 519 520 /* Line status inquiry for drivers */ 521 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset); 522 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset); 523 524 /* Sleep persistence inquiry for drivers */ 525 bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset); 526 bool gpiochip_line_is_valid(const struct gpio_chip *chip, unsigned int offset); 527 528 /* get driver data */ 529 void *gpiochip_get_data(struct gpio_chip *chip); 530 531 struct bgpio_pdata { 532 const char *label; 533 int base; 534 int ngpio; 535 }; 536 537 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 538 539 void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chip, 540 unsigned int parent_hwirq, 541 unsigned int parent_type); 542 void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip, 543 unsigned int parent_hwirq, 544 unsigned int parent_type); 545 546 #else 547 548 static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chip, 549 unsigned int parent_hwirq, 550 unsigned int parent_type) 551 { 552 return NULL; 553 } 554 555 static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip, 556 unsigned int parent_hwirq, 557 unsigned int parent_type) 558 { 559 return NULL; 560 } 561 562 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ 563 564 int bgpio_init(struct gpio_chip *gc, struct device *dev, 565 unsigned long sz, void __iomem *dat, void __iomem *set, 566 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 567 unsigned long flags); 568 569 #define BGPIOF_BIG_ENDIAN BIT(0) 570 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 571 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 572 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 573 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 574 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 575 576 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, 577 irq_hw_number_t hwirq); 578 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq); 579 580 int gpiochip_irq_domain_activate(struct irq_domain *domain, 581 struct irq_data *data, bool reserve); 582 void gpiochip_irq_domain_deactivate(struct irq_domain *domain, 583 struct irq_data *data); 584 585 void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip, 586 struct irq_chip *irqchip, 587 unsigned int parent_irq); 588 589 int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip, 590 struct irq_chip *irqchip, 591 unsigned int first_irq, 592 irq_flow_handler_t handler, 593 unsigned int type, 594 bool threaded, 595 struct lock_class_key *lock_key, 596 struct lock_class_key *request_key); 597 598 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip, 599 unsigned int offset); 600 601 #ifdef CONFIG_LOCKDEP 602 603 /* 604 * Lockdep requires that each irqchip instance be created with a 605 * unique key so as to avoid unnecessary warnings. This upfront 606 * boilerplate static inlines provides such a key for each 607 * unique instance. 608 */ 609 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip, 610 struct irq_chip *irqchip, 611 unsigned int first_irq, 612 irq_flow_handler_t handler, 613 unsigned int type) 614 { 615 static struct lock_class_key lock_key; 616 static struct lock_class_key request_key; 617 618 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, 619 handler, type, false, 620 &lock_key, &request_key); 621 } 622 623 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip, 624 struct irq_chip *irqchip, 625 unsigned int first_irq, 626 irq_flow_handler_t handler, 627 unsigned int type) 628 { 629 630 static struct lock_class_key lock_key; 631 static struct lock_class_key request_key; 632 633 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, 634 handler, type, true, 635 &lock_key, &request_key); 636 } 637 #else /* ! CONFIG_LOCKDEP */ 638 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip, 639 struct irq_chip *irqchip, 640 unsigned int first_irq, 641 irq_flow_handler_t handler, 642 unsigned int type) 643 { 644 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, 645 handler, type, false, NULL, NULL); 646 } 647 648 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip, 649 struct irq_chip *irqchip, 650 unsigned int first_irq, 651 irq_flow_handler_t handler, 652 unsigned int type) 653 { 654 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, 655 handler, type, true, NULL, NULL); 656 } 657 #endif /* CONFIG_LOCKDEP */ 658 659 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset); 660 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset); 661 int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset, 662 unsigned long config); 663 664 /** 665 * struct gpio_pin_range - pin range controlled by a gpio chip 666 * @node: list for maintaining set of pin ranges, used internally 667 * @pctldev: pinctrl device which handles corresponding pins 668 * @range: actual range of pins controlled by a gpio controller 669 */ 670 struct gpio_pin_range { 671 struct list_head node; 672 struct pinctrl_dev *pctldev; 673 struct pinctrl_gpio_range range; 674 }; 675 676 #ifdef CONFIG_PINCTRL 677 678 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, 679 unsigned int gpio_offset, unsigned int pin_offset, 680 unsigned int npins); 681 int gpiochip_add_pingroup_range(struct gpio_chip *chip, 682 struct pinctrl_dev *pctldev, 683 unsigned int gpio_offset, const char *pin_group); 684 void gpiochip_remove_pin_ranges(struct gpio_chip *chip); 685 686 #else /* ! CONFIG_PINCTRL */ 687 688 static inline int 689 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, 690 unsigned int gpio_offset, unsigned int pin_offset, 691 unsigned int npins) 692 { 693 return 0; 694 } 695 static inline int 696 gpiochip_add_pingroup_range(struct gpio_chip *chip, 697 struct pinctrl_dev *pctldev, 698 unsigned int gpio_offset, const char *pin_group) 699 { 700 return 0; 701 } 702 703 static inline void 704 gpiochip_remove_pin_ranges(struct gpio_chip *chip) 705 { 706 } 707 708 #endif /* CONFIG_PINCTRL */ 709 710 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, 711 unsigned int hwnum, 712 const char *label, 713 enum gpio_lookup_flags lflags, 714 enum gpiod_flags dflags); 715 void gpiochip_free_own_desc(struct gpio_desc *desc); 716 717 void devprop_gpiochip_set_names(struct gpio_chip *chip, 718 const struct fwnode_handle *fwnode); 719 720 #ifdef CONFIG_GPIOLIB 721 722 /* lock/unlock as IRQ */ 723 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset); 724 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset); 725 726 727 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 728 729 #else /* CONFIG_GPIOLIB */ 730 731 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 732 { 733 /* GPIO can never have been requested */ 734 WARN_ON(1); 735 return ERR_PTR(-ENODEV); 736 } 737 738 static inline int gpiochip_lock_as_irq(struct gpio_chip *chip, 739 unsigned int offset) 740 { 741 WARN_ON(1); 742 return -EINVAL; 743 } 744 745 static inline void gpiochip_unlock_as_irq(struct gpio_chip *chip, 746 unsigned int offset) 747 { 748 WARN_ON(1); 749 } 750 #endif /* CONFIG_GPIOLIB */ 751 752 #endif /* __LINUX_GPIO_DRIVER_H */ 753