1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_GPIO_DRIVER_H 3 #define __LINUX_GPIO_DRIVER_H 4 5 #include <linux/bits.h> 6 #include <linux/irqchip/chained_irq.h> 7 #include <linux/irqdomain.h> 8 #include <linux/irqhandler.h> 9 #include <linux/lockdep.h> 10 #include <linux/pinctrl/pinconf-generic.h> 11 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/property.h> 13 #include <linux/spinlock_types.h> 14 #include <linux/types.h> 15 16 #ifdef CONFIG_GENERIC_MSI_IRQ 17 #include <asm/msi.h> 18 #endif 19 20 struct device; 21 struct irq_chip; 22 struct irq_data; 23 struct module; 24 struct of_phandle_args; 25 struct pinctrl_dev; 26 struct seq_file; 27 28 struct gpio_chip; 29 struct gpio_desc; 30 struct gpio_device; 31 32 enum gpio_lookup_flags; 33 enum gpiod_flags; 34 35 union gpio_irq_fwspec { 36 struct irq_fwspec fwspec; 37 #ifdef CONFIG_GENERIC_MSI_IRQ 38 msi_alloc_info_t msiinfo; 39 #endif 40 }; 41 42 #define GPIO_LINE_DIRECTION_IN 1 43 #define GPIO_LINE_DIRECTION_OUT 0 44 45 /** 46 * struct gpio_irq_chip - GPIO interrupt controller 47 */ 48 struct gpio_irq_chip { 49 /** 50 * @chip: 51 * 52 * GPIO IRQ chip implementation, provided by GPIO driver. 53 */ 54 struct irq_chip *chip; 55 56 /** 57 * @domain: 58 * 59 * Interrupt translation domain; responsible for mapping between GPIO 60 * hwirq number and Linux IRQ number. 61 */ 62 struct irq_domain *domain; 63 64 /** 65 * @domain_ops: 66 * 67 * Table of interrupt domain operations for this IRQ chip. 68 */ 69 const struct irq_domain_ops *domain_ops; 70 71 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 72 /** 73 * @fwnode: 74 * 75 * Firmware node corresponding to this gpiochip/irqchip, necessary 76 * for hierarchical irqdomain support. 77 */ 78 struct fwnode_handle *fwnode; 79 80 /** 81 * @parent_domain: 82 * 83 * If non-NULL, will be set as the parent of this GPIO interrupt 84 * controller's IRQ domain to establish a hierarchical interrupt 85 * domain. The presence of this will activate the hierarchical 86 * interrupt support. 87 */ 88 struct irq_domain *parent_domain; 89 90 /** 91 * @child_to_parent_hwirq: 92 * 93 * This callback translates a child hardware IRQ offset to a parent 94 * hardware IRQ offset on a hierarchical interrupt chip. The child 95 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the 96 * ngpio field of struct gpio_chip) and the corresponding parent 97 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by 98 * the driver. The driver can calculate this from an offset or using 99 * a lookup table or whatever method is best for this chip. Return 100 * 0 on successful translation in the driver. 101 * 102 * If some ranges of hardware IRQs do not have a corresponding parent 103 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and 104 * @need_valid_mask to make these GPIO lines unavailable for 105 * translation. 106 */ 107 int (*child_to_parent_hwirq)(struct gpio_chip *gc, 108 unsigned int child_hwirq, 109 unsigned int child_type, 110 unsigned int *parent_hwirq, 111 unsigned int *parent_type); 112 113 /** 114 * @populate_parent_alloc_arg : 115 * 116 * This optional callback allocates and populates the specific struct 117 * for the parent's IRQ domain. If this is not specified, then 118 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell 119 * variant named &gpiochip_populate_parent_fwspec_fourcell is also 120 * available. 121 */ 122 int (*populate_parent_alloc_arg)(struct gpio_chip *gc, 123 union gpio_irq_fwspec *fwspec, 124 unsigned int parent_hwirq, 125 unsigned int parent_type); 126 127 /** 128 * @child_offset_to_irq: 129 * 130 * This optional callback is used to translate the child's GPIO line 131 * offset on the GPIO chip to an IRQ number for the GPIO to_irq() 132 * callback. If this is not specified, then a default callback will be 133 * provided that returns the line offset. 134 */ 135 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc, 136 unsigned int pin); 137 138 /** 139 * @child_irq_domain_ops: 140 * 141 * The IRQ domain operations that will be used for this GPIO IRQ 142 * chip. If no operations are provided, then default callbacks will 143 * be populated to setup the IRQ hierarchy. Some drivers need to 144 * supply their own translate function. 145 */ 146 struct irq_domain_ops child_irq_domain_ops; 147 #endif 148 149 /** 150 * @handler: 151 * 152 * The IRQ handler to use (often a predefined IRQ core function) for 153 * GPIO IRQs, provided by GPIO driver. 154 */ 155 irq_flow_handler_t handler; 156 157 /** 158 * @default_type: 159 * 160 * Default IRQ triggering type applied during GPIO driver 161 * initialization, provided by GPIO driver. 162 */ 163 unsigned int default_type; 164 165 /** 166 * @lock_key: 167 * 168 * Per GPIO IRQ chip lockdep class for IRQ lock. 169 */ 170 struct lock_class_key *lock_key; 171 172 /** 173 * @request_key: 174 * 175 * Per GPIO IRQ chip lockdep class for IRQ request. 176 */ 177 struct lock_class_key *request_key; 178 179 /** 180 * @parent_handler: 181 * 182 * The interrupt handler for the GPIO chip's parent interrupts, may be 183 * NULL if the parent interrupts are nested rather than cascaded. 184 */ 185 irq_flow_handler_t parent_handler; 186 187 union { 188 /** 189 * @parent_handler_data: 190 * 191 * If @per_parent_data is false, @parent_handler_data is a 192 * single pointer used as the data associated with every 193 * parent interrupt. 194 */ 195 void *parent_handler_data; 196 197 /** 198 * @parent_handler_data_array: 199 * 200 * If @per_parent_data is true, @parent_handler_data_array is 201 * an array of @num_parents pointers, and is used to associate 202 * different data for each parent. This cannot be NULL if 203 * @per_parent_data is true. 204 */ 205 void **parent_handler_data_array; 206 }; 207 208 /** 209 * @num_parents: 210 * 211 * The number of interrupt parents of a GPIO chip. 212 */ 213 unsigned int num_parents; 214 215 /** 216 * @parents: 217 * 218 * A list of interrupt parents of a GPIO chip. This is owned by the 219 * driver, so the core will only reference this list, not modify it. 220 */ 221 unsigned int *parents; 222 223 /** 224 * @map: 225 * 226 * A list of interrupt parents for each line of a GPIO chip. 227 */ 228 unsigned int *map; 229 230 /** 231 * @threaded: 232 * 233 * True if set the interrupt handling uses nested threads. 234 */ 235 bool threaded; 236 237 /** 238 * @per_parent_data: 239 * 240 * True if parent_handler_data_array describes a @num_parents 241 * sized array to be used as parent data. 242 */ 243 bool per_parent_data; 244 245 /** 246 * @initialized: 247 * 248 * Flag to track GPIO chip irq member's initialization. 249 * This flag will make sure GPIO chip irq members are not used 250 * before they are initialized. 251 */ 252 bool initialized; 253 254 /** 255 * @init_hw: optional routine to initialize hardware before 256 * an IRQ chip will be added. This is quite useful when 257 * a particular driver wants to clear IRQ related registers 258 * in order to avoid undesired events. 259 */ 260 int (*init_hw)(struct gpio_chip *gc); 261 262 /** 263 * @init_valid_mask: optional routine to initialize @valid_mask, to be 264 * used if not all GPIO lines are valid interrupts. Sometimes some 265 * lines just cannot fire interrupts, and this routine, when defined, 266 * is passed a bitmap in "valid_mask" and it will have ngpios 267 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can 268 * then directly set some bits to "0" if they cannot be used for 269 * interrupts. 270 */ 271 void (*init_valid_mask)(struct gpio_chip *gc, 272 unsigned long *valid_mask, 273 unsigned int ngpios); 274 275 /** 276 * @valid_mask: 277 * 278 * If not %NULL, holds bitmask of GPIOs which are valid to be included 279 * in IRQ domain of the chip. 280 */ 281 unsigned long *valid_mask; 282 283 /** 284 * @first: 285 * 286 * Required for static IRQ allocation. If set, irq_domain_add_simple() 287 * will allocate and map all IRQs during initialization. 288 */ 289 unsigned int first; 290 291 /** 292 * @irq_enable: 293 * 294 * Store old irq_chip irq_enable callback 295 */ 296 void (*irq_enable)(struct irq_data *data); 297 298 /** 299 * @irq_disable: 300 * 301 * Store old irq_chip irq_disable callback 302 */ 303 void (*irq_disable)(struct irq_data *data); 304 /** 305 * @irq_unmask: 306 * 307 * Store old irq_chip irq_unmask callback 308 */ 309 void (*irq_unmask)(struct irq_data *data); 310 311 /** 312 * @irq_mask: 313 * 314 * Store old irq_chip irq_mask callback 315 */ 316 void (*irq_mask)(struct irq_data *data); 317 }; 318 319 /** 320 * struct gpio_chip - abstract a GPIO controller 321 * @label: a functional name for the GPIO device, such as a part 322 * number or the name of the SoC IP-block implementing it. 323 * @gpiodev: the internal state holder, opaque struct 324 * @parent: optional parent device providing the GPIOs 325 * @fwnode: optional fwnode providing this controller's properties 326 * @owner: helps prevent removal of modules exporting active GPIOs 327 * @request: optional hook for chip-specific activation, such as 328 * enabling module power and clock; may sleep 329 * @free: optional hook for chip-specific deactivation, such as 330 * disabling module power and clock; may sleep 331 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 332 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN), 333 * or negative error. It is recommended to always implement this 334 * function, even on input-only or output-only gpio chips. 335 * @direction_input: configures signal "offset" as input, or returns error 336 * This can be omitted on input-only or output-only gpio chips. 337 * @direction_output: configures signal "offset" as output, or returns error 338 * This can be omitted on input-only or output-only gpio chips. 339 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 340 * @get_multiple: reads values for multiple signals defined by "mask" and 341 * stores them in "bits", returns 0 on success or negative error 342 * @set: assigns output value for signal "offset" 343 * @set_multiple: assigns output values for multiple signals defined by "mask" 344 * @set_config: optional hook for all kinds of settings. Uses the same 345 * packed config format as generic pinconf. 346 * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings; 347 * implementation may not sleep 348 * @dbg_show: optional routine to show contents in debugfs; default code 349 * will be used when this is omitted, but custom code can show extra 350 * state (such as pullup/pulldown configuration). 351 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if 352 * not all GPIOs are valid. 353 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when 354 * requires special mapping of the pins that provides GPIO functionality. 355 * It is called after adding GPIO chip and before adding IRQ chip. 356 * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to 357 * enable hardware timestamp. 358 * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to 359 * disable hardware timestamp. 360 * @base: identifies the first GPIO number handled by this chip; 361 * or, if negative during registration, requests dynamic ID allocation. 362 * DEPRECATION: providing anything non-negative and nailing the base 363 * offset of GPIO chips is deprecated. Please pass -1 as base to 364 * let gpiolib select the chip base in all possible cases. We want to 365 * get rid of the static GPIO number space in the long run. 366 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 367 * handled is (base + ngpio - 1). 368 * @offset: when multiple gpio chips belong to the same device this 369 * can be used as offset within the device so friendly names can 370 * be properly assigned. 371 * @names: if set, must be an array of strings to use as alternative 372 * names for the GPIOs in this chip. Any entry in the array 373 * may be NULL if there is no alias for the GPIO, however the 374 * array must be @ngpio entries long. A name can include a single printk 375 * format specifier for an unsigned int. It is substituted by the actual 376 * number of the gpio. 377 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 378 * must while accessing GPIO expander chips over I2C or SPI. This 379 * implies that if the chip supports IRQs, these IRQs need to be threaded 380 * as the chip access may sleep when e.g. reading out the IRQ status 381 * registers. 382 * @read_reg: reader function for generic GPIO 383 * @write_reg: writer function for generic GPIO 384 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing 385 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the 386 * generic GPIO core. It is for internal housekeeping only. 387 * @reg_dat: data (in) register for generic GPIO 388 * @reg_set: output set register (out=high) for generic GPIO 389 * @reg_clr: output clear register (out=low) for generic GPIO 390 * @reg_dir_out: direction out setting register for generic GPIO 391 * @reg_dir_in: direction in setting register for generic GPIO 392 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 393 * be read and we need to rely on out internal state tracking. 394 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 395 * <register width> * 8 396 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 397 * shadowed and real data registers writes together. 398 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 399 * safely. 400 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 401 * direction safely. A "1" in this word means the line is set as 402 * output. 403 * 404 * A gpio_chip can help platforms abstract various sources of GPIOs so 405 * they can all be accessed through a common programming interface. 406 * Example sources would be SOC controllers, FPGAs, multifunction 407 * chips, dedicated GPIO expanders, and so on. 408 * 409 * Each chip controls a number of signals, identified in method calls 410 * by "offset" values in the range 0..(@ngpio - 1). When those signals 411 * are referenced through calls like gpio_get_value(gpio), the offset 412 * is calculated by subtracting @base from the gpio number. 413 */ 414 struct gpio_chip { 415 const char *label; 416 struct gpio_device *gpiodev; 417 struct device *parent; 418 struct fwnode_handle *fwnode; 419 struct module *owner; 420 421 int (*request)(struct gpio_chip *gc, 422 unsigned int offset); 423 void (*free)(struct gpio_chip *gc, 424 unsigned int offset); 425 int (*get_direction)(struct gpio_chip *gc, 426 unsigned int offset); 427 int (*direction_input)(struct gpio_chip *gc, 428 unsigned int offset); 429 int (*direction_output)(struct gpio_chip *gc, 430 unsigned int offset, int value); 431 int (*get)(struct gpio_chip *gc, 432 unsigned int offset); 433 int (*get_multiple)(struct gpio_chip *gc, 434 unsigned long *mask, 435 unsigned long *bits); 436 void (*set)(struct gpio_chip *gc, 437 unsigned int offset, int value); 438 void (*set_multiple)(struct gpio_chip *gc, 439 unsigned long *mask, 440 unsigned long *bits); 441 int (*set_config)(struct gpio_chip *gc, 442 unsigned int offset, 443 unsigned long config); 444 int (*to_irq)(struct gpio_chip *gc, 445 unsigned int offset); 446 447 void (*dbg_show)(struct seq_file *s, 448 struct gpio_chip *gc); 449 450 int (*init_valid_mask)(struct gpio_chip *gc, 451 unsigned long *valid_mask, 452 unsigned int ngpios); 453 454 int (*add_pin_ranges)(struct gpio_chip *gc); 455 456 int (*en_hw_timestamp)(struct gpio_chip *gc, 457 u32 offset, 458 unsigned long flags); 459 int (*dis_hw_timestamp)(struct gpio_chip *gc, 460 u32 offset, 461 unsigned long flags); 462 int base; 463 u16 ngpio; 464 u16 offset; 465 const char *const *names; 466 bool can_sleep; 467 468 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 469 unsigned long (*read_reg)(void __iomem *reg); 470 void (*write_reg)(void __iomem *reg, unsigned long data); 471 bool be_bits; 472 void __iomem *reg_dat; 473 void __iomem *reg_set; 474 void __iomem *reg_clr; 475 void __iomem *reg_dir_out; 476 void __iomem *reg_dir_in; 477 bool bgpio_dir_unreadable; 478 int bgpio_bits; 479 raw_spinlock_t bgpio_lock; 480 unsigned long bgpio_data; 481 unsigned long bgpio_dir; 482 #endif /* CONFIG_GPIO_GENERIC */ 483 484 #ifdef CONFIG_GPIOLIB_IRQCHIP 485 /* 486 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 487 * to handle IRQs for most practical cases. 488 */ 489 490 /** 491 * @irq: 492 * 493 * Integrates interrupt chip functionality with the GPIO chip. Can be 494 * used to handle IRQs for most practical cases. 495 */ 496 struct gpio_irq_chip irq; 497 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 498 499 /** 500 * @valid_mask: 501 * 502 * If not %NULL, holds bitmask of GPIOs which are valid to be used 503 * from the chip. 504 */ 505 unsigned long *valid_mask; 506 507 #if defined(CONFIG_OF_GPIO) 508 /* 509 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in 510 * the device tree automatically may have an OF translation 511 */ 512 513 /** 514 * @of_gpio_n_cells: 515 * 516 * Number of cells used to form the GPIO specifier. 517 */ 518 unsigned int of_gpio_n_cells; 519 520 /** 521 * @of_xlate: 522 * 523 * Callback to translate a device tree GPIO specifier into a chip- 524 * relative GPIO number and flags. 525 */ 526 int (*of_xlate)(struct gpio_chip *gc, 527 const struct of_phandle_args *gpiospec, u32 *flags); 528 #endif /* CONFIG_OF_GPIO */ 529 }; 530 531 extern const char *gpiochip_is_requested(struct gpio_chip *gc, 532 unsigned int offset); 533 534 /** 535 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range 536 * @chip: the chip to query 537 * @i: loop variable 538 * @base: first GPIO in the range 539 * @size: amount of GPIOs to check starting from @base 540 * @label: label of current GPIO 541 */ 542 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \ 543 for (i = 0; i < size; i++) \ 544 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else 545 546 /* Iterates over all requested GPIO of the given @chip */ 547 #define for_each_requested_gpio(chip, i, label) \ 548 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label) 549 550 /* add/remove chips */ 551 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, 552 struct lock_class_key *lock_key, 553 struct lock_class_key *request_key); 554 555 /** 556 * gpiochip_add_data() - register a gpio_chip 557 * @gc: the chip to register, with gc->base initialized 558 * @data: driver-private data associated with this chip 559 * 560 * Context: potentially before irqs will work 561 * 562 * When gpiochip_add_data() is called very early during boot, so that GPIOs 563 * can be freely used, the gc->parent device must be registered before 564 * the gpio framework's arch_initcall(). Otherwise sysfs initialization 565 * for GPIOs will fail rudely. 566 * 567 * gpiochip_add_data() must only be called after gpiolib initialization, 568 * i.e. after core_initcall(). 569 * 570 * If gc->base is negative, this requests dynamic assignment of 571 * a range of valid GPIOs. 572 * 573 * Returns: 574 * A negative errno if the chip can't be registered, such as because the 575 * gc->base is invalid or already associated with a different chip. 576 * Otherwise it returns zero as a success code. 577 */ 578 #ifdef CONFIG_LOCKDEP 579 #define gpiochip_add_data(gc, data) ({ \ 580 static struct lock_class_key lock_key; \ 581 static struct lock_class_key request_key; \ 582 gpiochip_add_data_with_key(gc, data, &lock_key, \ 583 &request_key); \ 584 }) 585 #define devm_gpiochip_add_data(dev, gc, data) ({ \ 586 static struct lock_class_key lock_key; \ 587 static struct lock_class_key request_key; \ 588 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \ 589 &request_key); \ 590 }) 591 #else 592 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL) 593 #define devm_gpiochip_add_data(dev, gc, data) \ 594 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL) 595 #endif /* CONFIG_LOCKDEP */ 596 597 static inline int gpiochip_add(struct gpio_chip *gc) 598 { 599 return gpiochip_add_data(gc, NULL); 600 } 601 extern void gpiochip_remove(struct gpio_chip *gc); 602 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data, 603 struct lock_class_key *lock_key, 604 struct lock_class_key *request_key); 605 606 extern struct gpio_chip *gpiochip_find(void *data, 607 int (*match)(struct gpio_chip *gc, void *data)); 608 609 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset); 610 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset); 611 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset); 612 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset); 613 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); 614 615 /* irq_data versions of the above */ 616 int gpiochip_irq_reqres(struct irq_data *data); 617 void gpiochip_irq_relres(struct irq_data *data); 618 619 /* Paste this in your irq_chip structure */ 620 #define GPIOCHIP_IRQ_RESOURCE_HELPERS \ 621 .irq_request_resources = gpiochip_irq_reqres, \ 622 .irq_release_resources = gpiochip_irq_relres 623 624 static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq, 625 const struct irq_chip *chip) 626 { 627 /* Yes, dropping const is ugly, but it isn't like we have a choice */ 628 girq->chip = (struct irq_chip *)chip; 629 } 630 631 /* Line status inquiry for drivers */ 632 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); 633 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); 634 635 /* Sleep persistence inquiry for drivers */ 636 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset); 637 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset); 638 639 /* get driver data */ 640 void *gpiochip_get_data(struct gpio_chip *gc); 641 642 struct bgpio_pdata { 643 const char *label; 644 int base; 645 int ngpio; 646 }; 647 648 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 649 650 int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, 651 union gpio_irq_fwspec *gfwspec, 652 unsigned int parent_hwirq, 653 unsigned int parent_type); 654 int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, 655 union gpio_irq_fwspec *gfwspec, 656 unsigned int parent_hwirq, 657 unsigned int parent_type); 658 659 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ 660 661 int bgpio_init(struct gpio_chip *gc, struct device *dev, 662 unsigned long sz, void __iomem *dat, void __iomem *set, 663 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 664 unsigned long flags); 665 666 #define BGPIOF_BIG_ENDIAN BIT(0) 667 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 668 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 669 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 670 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 671 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 672 #define BGPIOF_NO_SET_ON_INPUT BIT(6) 673 674 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, 675 irq_hw_number_t hwirq); 676 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq); 677 678 int gpiochip_irq_domain_activate(struct irq_domain *domain, 679 struct irq_data *data, bool reserve); 680 void gpiochip_irq_domain_deactivate(struct irq_domain *domain, 681 struct irq_data *data); 682 683 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc, 684 unsigned int offset); 685 686 #ifdef CONFIG_GPIOLIB_IRQCHIP 687 int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 688 struct irq_domain *domain); 689 #else 690 691 #include <asm/bug.h> 692 #include <asm/errno.h> 693 694 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 695 struct irq_domain *domain) 696 { 697 WARN_ON(1); 698 return -EINVAL; 699 } 700 #endif 701 702 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset); 703 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset); 704 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset, 705 unsigned long config); 706 707 /** 708 * struct gpio_pin_range - pin range controlled by a gpio chip 709 * @node: list for maintaining set of pin ranges, used internally 710 * @pctldev: pinctrl device which handles corresponding pins 711 * @range: actual range of pins controlled by a gpio controller 712 */ 713 struct gpio_pin_range { 714 struct list_head node; 715 struct pinctrl_dev *pctldev; 716 struct pinctrl_gpio_range range; 717 }; 718 719 #ifdef CONFIG_PINCTRL 720 721 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 722 unsigned int gpio_offset, unsigned int pin_offset, 723 unsigned int npins); 724 int gpiochip_add_pingroup_range(struct gpio_chip *gc, 725 struct pinctrl_dev *pctldev, 726 unsigned int gpio_offset, const char *pin_group); 727 void gpiochip_remove_pin_ranges(struct gpio_chip *gc); 728 729 #else /* ! CONFIG_PINCTRL */ 730 731 static inline int 732 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 733 unsigned int gpio_offset, unsigned int pin_offset, 734 unsigned int npins) 735 { 736 return 0; 737 } 738 static inline int 739 gpiochip_add_pingroup_range(struct gpio_chip *gc, 740 struct pinctrl_dev *pctldev, 741 unsigned int gpio_offset, const char *pin_group) 742 { 743 return 0; 744 } 745 746 static inline void 747 gpiochip_remove_pin_ranges(struct gpio_chip *gc) 748 { 749 } 750 751 #endif /* CONFIG_PINCTRL */ 752 753 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc, 754 unsigned int hwnum, 755 const char *label, 756 enum gpio_lookup_flags lflags, 757 enum gpiod_flags dflags); 758 void gpiochip_free_own_desc(struct gpio_desc *desc); 759 760 #ifdef CONFIG_GPIOLIB 761 762 /* lock/unlock as IRQ */ 763 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset); 764 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset); 765 766 767 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 768 769 #else /* CONFIG_GPIOLIB */ 770 771 #include <linux/err.h> 772 773 #include <asm/bug.h> 774 775 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 776 { 777 /* GPIO can never have been requested */ 778 WARN_ON(1); 779 return ERR_PTR(-ENODEV); 780 } 781 782 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc, 783 unsigned int offset) 784 { 785 WARN_ON(1); 786 return -EINVAL; 787 } 788 789 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc, 790 unsigned int offset) 791 { 792 WARN_ON(1); 793 } 794 #endif /* CONFIG_GPIOLIB */ 795 796 #define for_each_gpiochip_node(dev, child) \ 797 device_for_each_child_node(dev, child) \ 798 if (!fwnode_property_present(child, "gpio-controller")) {} else 799 800 static inline unsigned int gpiochip_node_count(struct device *dev) 801 { 802 struct fwnode_handle *child; 803 unsigned int count = 0; 804 805 for_each_gpiochip_node(dev, child) 806 count++; 807 808 return count; 809 } 810 811 static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev) 812 { 813 struct fwnode_handle *fwnode; 814 815 for_each_gpiochip_node(dev, fwnode) 816 return fwnode; 817 818 return NULL; 819 } 820 821 #endif /* __LINUX_GPIO_DRIVER_H */ 822