1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_GPIO_DRIVER_H 3 #define __LINUX_GPIO_DRIVER_H 4 5 #include <linux/device.h> 6 #include <linux/types.h> 7 #include <linux/irq.h> 8 #include <linux/irqchip/chained_irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/lockdep.h> 11 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 14 struct gpio_desc; 15 struct of_phandle_args; 16 struct device_node; 17 struct seq_file; 18 struct gpio_device; 19 struct module; 20 enum gpiod_flags; 21 enum gpio_lookup_flags; 22 23 struct gpio_chip; 24 25 #define GPIO_LINE_DIRECTION_IN 1 26 #define GPIO_LINE_DIRECTION_OUT 0 27 28 /** 29 * struct gpio_irq_chip - GPIO interrupt controller 30 */ 31 struct gpio_irq_chip { 32 /** 33 * @chip: 34 * 35 * GPIO IRQ chip implementation, provided by GPIO driver. 36 */ 37 struct irq_chip *chip; 38 39 /** 40 * @domain: 41 * 42 * Interrupt translation domain; responsible for mapping between GPIO 43 * hwirq number and Linux IRQ number. 44 */ 45 struct irq_domain *domain; 46 47 /** 48 * @domain_ops: 49 * 50 * Table of interrupt domain operations for this IRQ chip. 51 */ 52 const struct irq_domain_ops *domain_ops; 53 54 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 55 /** 56 * @fwnode: 57 * 58 * Firmware node corresponding to this gpiochip/irqchip, necessary 59 * for hierarchical irqdomain support. 60 */ 61 struct fwnode_handle *fwnode; 62 63 /** 64 * @parent_domain: 65 * 66 * If non-NULL, will be set as the parent of this GPIO interrupt 67 * controller's IRQ domain to establish a hierarchical interrupt 68 * domain. The presence of this will activate the hierarchical 69 * interrupt support. 70 */ 71 struct irq_domain *parent_domain; 72 73 /** 74 * @child_to_parent_hwirq: 75 * 76 * This callback translates a child hardware IRQ offset to a parent 77 * hardware IRQ offset on a hierarchical interrupt chip. The child 78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the 79 * ngpio field of struct gpio_chip) and the corresponding parent 80 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by 81 * the driver. The driver can calculate this from an offset or using 82 * a lookup table or whatever method is best for this chip. Return 83 * 0 on successful translation in the driver. 84 * 85 * If some ranges of hardware IRQs do not have a corresponding parent 86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and 87 * @need_valid_mask to make these GPIO lines unavailable for 88 * translation. 89 */ 90 int (*child_to_parent_hwirq)(struct gpio_chip *gc, 91 unsigned int child_hwirq, 92 unsigned int child_type, 93 unsigned int *parent_hwirq, 94 unsigned int *parent_type); 95 96 /** 97 * @populate_parent_alloc_arg : 98 * 99 * This optional callback allocates and populates the specific struct 100 * for the parent's IRQ domain. If this is not specified, then 101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell 102 * variant named &gpiochip_populate_parent_fwspec_fourcell is also 103 * available. 104 */ 105 void *(*populate_parent_alloc_arg)(struct gpio_chip *gc, 106 unsigned int parent_hwirq, 107 unsigned int parent_type); 108 109 /** 110 * @child_offset_to_irq: 111 * 112 * This optional callback is used to translate the child's GPIO line 113 * offset on the GPIO chip to an IRQ number for the GPIO to_irq() 114 * callback. If this is not specified, then a default callback will be 115 * provided that returns the line offset. 116 */ 117 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc, 118 unsigned int pin); 119 120 /** 121 * @child_irq_domain_ops: 122 * 123 * The IRQ domain operations that will be used for this GPIO IRQ 124 * chip. If no operations are provided, then default callbacks will 125 * be populated to setup the IRQ hierarchy. Some drivers need to 126 * supply their own translate function. 127 */ 128 struct irq_domain_ops child_irq_domain_ops; 129 #endif 130 131 /** 132 * @handler: 133 * 134 * The IRQ handler to use (often a predefined IRQ core function) for 135 * GPIO IRQs, provided by GPIO driver. 136 */ 137 irq_flow_handler_t handler; 138 139 /** 140 * @default_type: 141 * 142 * Default IRQ triggering type applied during GPIO driver 143 * initialization, provided by GPIO driver. 144 */ 145 unsigned int default_type; 146 147 /** 148 * @lock_key: 149 * 150 * Per GPIO IRQ chip lockdep class for IRQ lock. 151 */ 152 struct lock_class_key *lock_key; 153 154 /** 155 * @request_key: 156 * 157 * Per GPIO IRQ chip lockdep class for IRQ request. 158 */ 159 struct lock_class_key *request_key; 160 161 /** 162 * @parent_handler: 163 * 164 * The interrupt handler for the GPIO chip's parent interrupts, may be 165 * NULL if the parent interrupts are nested rather than cascaded. 166 */ 167 irq_flow_handler_t parent_handler; 168 169 /** 170 * @parent_handler_data: 171 * @parent_handler_data_array: 172 * 173 * Data associated, and passed to, the handler for the parent 174 * interrupt. Can either be a single pointer if @per_parent_data 175 * is false, or an array of @num_parents pointers otherwise. If 176 * @per_parent_data is true, @parent_handler_data_array cannot be 177 * NULL. 178 */ 179 union { 180 void *parent_handler_data; 181 void **parent_handler_data_array; 182 }; 183 184 /** 185 * @num_parents: 186 * 187 * The number of interrupt parents of a GPIO chip. 188 */ 189 unsigned int num_parents; 190 191 /** 192 * @parents: 193 * 194 * A list of interrupt parents of a GPIO chip. This is owned by the 195 * driver, so the core will only reference this list, not modify it. 196 */ 197 unsigned int *parents; 198 199 /** 200 * @map: 201 * 202 * A list of interrupt parents for each line of a GPIO chip. 203 */ 204 unsigned int *map; 205 206 /** 207 * @threaded: 208 * 209 * True if set the interrupt handling uses nested threads. 210 */ 211 bool threaded; 212 213 /** 214 * @per_parent_data: 215 * 216 * True if parent_handler_data_array describes a @num_parents 217 * sized array to be used as parent data. 218 */ 219 bool per_parent_data; 220 221 /** 222 * @init_hw: optional routine to initialize hardware before 223 * an IRQ chip will be added. This is quite useful when 224 * a particular driver wants to clear IRQ related registers 225 * in order to avoid undesired events. 226 */ 227 int (*init_hw)(struct gpio_chip *gc); 228 229 /** 230 * @init_valid_mask: optional routine to initialize @valid_mask, to be 231 * used if not all GPIO lines are valid interrupts. Sometimes some 232 * lines just cannot fire interrupts, and this routine, when defined, 233 * is passed a bitmap in "valid_mask" and it will have ngpios 234 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can 235 * then directly set some bits to "0" if they cannot be used for 236 * interrupts. 237 */ 238 void (*init_valid_mask)(struct gpio_chip *gc, 239 unsigned long *valid_mask, 240 unsigned int ngpios); 241 242 /** 243 * @valid_mask: 244 * 245 * If not %NULL, holds bitmask of GPIOs which are valid to be included 246 * in IRQ domain of the chip. 247 */ 248 unsigned long *valid_mask; 249 250 /** 251 * @first: 252 * 253 * Required for static IRQ allocation. If set, irq_domain_add_simple() 254 * will allocate and map all IRQs during initialization. 255 */ 256 unsigned int first; 257 258 /** 259 * @irq_enable: 260 * 261 * Store old irq_chip irq_enable callback 262 */ 263 void (*irq_enable)(struct irq_data *data); 264 265 /** 266 * @irq_disable: 267 * 268 * Store old irq_chip irq_disable callback 269 */ 270 void (*irq_disable)(struct irq_data *data); 271 /** 272 * @irq_unmask: 273 * 274 * Store old irq_chip irq_unmask callback 275 */ 276 void (*irq_unmask)(struct irq_data *data); 277 278 /** 279 * @irq_mask: 280 * 281 * Store old irq_chip irq_mask callback 282 */ 283 void (*irq_mask)(struct irq_data *data); 284 }; 285 286 /** 287 * struct gpio_chip - abstract a GPIO controller 288 * @label: a functional name for the GPIO device, such as a part 289 * number or the name of the SoC IP-block implementing it. 290 * @gpiodev: the internal state holder, opaque struct 291 * @parent: optional parent device providing the GPIOs 292 * @owner: helps prevent removal of modules exporting active GPIOs 293 * @request: optional hook for chip-specific activation, such as 294 * enabling module power and clock; may sleep 295 * @free: optional hook for chip-specific deactivation, such as 296 * disabling module power and clock; may sleep 297 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 298 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN), 299 * or negative error. It is recommended to always implement this 300 * function, even on input-only or output-only gpio chips. 301 * @direction_input: configures signal "offset" as input, or returns error 302 * This can be omitted on input-only or output-only gpio chips. 303 * @direction_output: configures signal "offset" as output, or returns error 304 * This can be omitted on input-only or output-only gpio chips. 305 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 306 * @get_multiple: reads values for multiple signals defined by "mask" and 307 * stores them in "bits", returns 0 on success or negative error 308 * @set: assigns output value for signal "offset" 309 * @set_multiple: assigns output values for multiple signals defined by "mask" 310 * @set_config: optional hook for all kinds of settings. Uses the same 311 * packed config format as generic pinconf. 312 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings; 313 * implementation may not sleep 314 * @dbg_show: optional routine to show contents in debugfs; default code 315 * will be used when this is omitted, but custom code can show extra 316 * state (such as pullup/pulldown configuration). 317 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if 318 * not all GPIOs are valid. 319 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when 320 * requires special mapping of the pins that provides GPIO functionality. 321 * It is called after adding GPIO chip and before adding IRQ chip. 322 * @base: identifies the first GPIO number handled by this chip; 323 * or, if negative during registration, requests dynamic ID allocation. 324 * DEPRECATION: providing anything non-negative and nailing the base 325 * offset of GPIO chips is deprecated. Please pass -1 as base to 326 * let gpiolib select the chip base in all possible cases. We want to 327 * get rid of the static GPIO number space in the long run. 328 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 329 * handled is (base + ngpio - 1). 330 * @offset: when multiple gpio chips belong to the same device this 331 * can be used as offset within the device so friendly names can 332 * be properly assigned. 333 * @names: if set, must be an array of strings to use as alternative 334 * names for the GPIOs in this chip. Any entry in the array 335 * may be NULL if there is no alias for the GPIO, however the 336 * array must be @ngpio entries long. A name can include a single printk 337 * format specifier for an unsigned int. It is substituted by the actual 338 * number of the gpio. 339 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 340 * must while accessing GPIO expander chips over I2C or SPI. This 341 * implies that if the chip supports IRQs, these IRQs need to be threaded 342 * as the chip access may sleep when e.g. reading out the IRQ status 343 * registers. 344 * @read_reg: reader function for generic GPIO 345 * @write_reg: writer function for generic GPIO 346 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing 347 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the 348 * generic GPIO core. It is for internal housekeeping only. 349 * @reg_dat: data (in) register for generic GPIO 350 * @reg_set: output set register (out=high) for generic GPIO 351 * @reg_clr: output clear register (out=low) for generic GPIO 352 * @reg_dir_out: direction out setting register for generic GPIO 353 * @reg_dir_in: direction in setting register for generic GPIO 354 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 355 * be read and we need to rely on out internal state tracking. 356 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 357 * <register width> * 8 358 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 359 * shadowed and real data registers writes together. 360 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 361 * safely. 362 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 363 * direction safely. A "1" in this word means the line is set as 364 * output. 365 * 366 * A gpio_chip can help platforms abstract various sources of GPIOs so 367 * they can all be accessed through a common programming interface. 368 * Example sources would be SOC controllers, FPGAs, multifunction 369 * chips, dedicated GPIO expanders, and so on. 370 * 371 * Each chip controls a number of signals, identified in method calls 372 * by "offset" values in the range 0..(@ngpio - 1). When those signals 373 * are referenced through calls like gpio_get_value(gpio), the offset 374 * is calculated by subtracting @base from the gpio number. 375 */ 376 struct gpio_chip { 377 const char *label; 378 struct gpio_device *gpiodev; 379 struct device *parent; 380 struct module *owner; 381 382 int (*request)(struct gpio_chip *gc, 383 unsigned int offset); 384 void (*free)(struct gpio_chip *gc, 385 unsigned int offset); 386 int (*get_direction)(struct gpio_chip *gc, 387 unsigned int offset); 388 int (*direction_input)(struct gpio_chip *gc, 389 unsigned int offset); 390 int (*direction_output)(struct gpio_chip *gc, 391 unsigned int offset, int value); 392 int (*get)(struct gpio_chip *gc, 393 unsigned int offset); 394 int (*get_multiple)(struct gpio_chip *gc, 395 unsigned long *mask, 396 unsigned long *bits); 397 void (*set)(struct gpio_chip *gc, 398 unsigned int offset, int value); 399 void (*set_multiple)(struct gpio_chip *gc, 400 unsigned long *mask, 401 unsigned long *bits); 402 int (*set_config)(struct gpio_chip *gc, 403 unsigned int offset, 404 unsigned long config); 405 int (*to_irq)(struct gpio_chip *gc, 406 unsigned int offset); 407 408 void (*dbg_show)(struct seq_file *s, 409 struct gpio_chip *gc); 410 411 int (*init_valid_mask)(struct gpio_chip *gc, 412 unsigned long *valid_mask, 413 unsigned int ngpios); 414 415 int (*add_pin_ranges)(struct gpio_chip *gc); 416 417 int base; 418 u16 ngpio; 419 u16 offset; 420 const char *const *names; 421 bool can_sleep; 422 423 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 424 unsigned long (*read_reg)(void __iomem *reg); 425 void (*write_reg)(void __iomem *reg, unsigned long data); 426 bool be_bits; 427 void __iomem *reg_dat; 428 void __iomem *reg_set; 429 void __iomem *reg_clr; 430 void __iomem *reg_dir_out; 431 void __iomem *reg_dir_in; 432 bool bgpio_dir_unreadable; 433 int bgpio_bits; 434 spinlock_t bgpio_lock; 435 unsigned long bgpio_data; 436 unsigned long bgpio_dir; 437 #endif /* CONFIG_GPIO_GENERIC */ 438 439 #ifdef CONFIG_GPIOLIB_IRQCHIP 440 /* 441 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 442 * to handle IRQs for most practical cases. 443 */ 444 445 /** 446 * @irq: 447 * 448 * Integrates interrupt chip functionality with the GPIO chip. Can be 449 * used to handle IRQs for most practical cases. 450 */ 451 struct gpio_irq_chip irq; 452 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 453 454 /** 455 * @valid_mask: 456 * 457 * If not %NULL, holds bitmask of GPIOs which are valid to be used 458 * from the chip. 459 */ 460 unsigned long *valid_mask; 461 462 #if defined(CONFIG_OF_GPIO) 463 /* 464 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in 465 * the device tree automatically may have an OF translation 466 */ 467 468 /** 469 * @of_node: 470 * 471 * Pointer to a device tree node representing this GPIO controller. 472 */ 473 struct device_node *of_node; 474 475 /** 476 * @of_gpio_n_cells: 477 * 478 * Number of cells used to form the GPIO specifier. 479 */ 480 unsigned int of_gpio_n_cells; 481 482 /** 483 * @of_xlate: 484 * 485 * Callback to translate a device tree GPIO specifier into a chip- 486 * relative GPIO number and flags. 487 */ 488 int (*of_xlate)(struct gpio_chip *gc, 489 const struct of_phandle_args *gpiospec, u32 *flags); 490 #endif /* CONFIG_OF_GPIO */ 491 }; 492 493 extern const char *gpiochip_is_requested(struct gpio_chip *gc, 494 unsigned int offset); 495 496 /** 497 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range 498 * @chip: the chip to query 499 * @i: loop variable 500 * @base: first GPIO in the range 501 * @size: amount of GPIOs to check starting from @base 502 * @label: label of current GPIO 503 */ 504 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \ 505 for (i = 0; i < size; i++) \ 506 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else 507 508 /* Iterates over all requested GPIO of the given @chip */ 509 #define for_each_requested_gpio(chip, i, label) \ 510 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label) 511 512 /* add/remove chips */ 513 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, 514 struct lock_class_key *lock_key, 515 struct lock_class_key *request_key); 516 517 /** 518 * gpiochip_add_data() - register a gpio_chip 519 * @gc: the chip to register, with gc->base initialized 520 * @data: driver-private data associated with this chip 521 * 522 * Context: potentially before irqs will work 523 * 524 * When gpiochip_add_data() is called very early during boot, so that GPIOs 525 * can be freely used, the gc->parent device must be registered before 526 * the gpio framework's arch_initcall(). Otherwise sysfs initialization 527 * for GPIOs will fail rudely. 528 * 529 * gpiochip_add_data() must only be called after gpiolib initialization, 530 * i.e. after core_initcall(). 531 * 532 * If gc->base is negative, this requests dynamic assignment of 533 * a range of valid GPIOs. 534 * 535 * Returns: 536 * A negative errno if the chip can't be registered, such as because the 537 * gc->base is invalid or already associated with a different chip. 538 * Otherwise it returns zero as a success code. 539 */ 540 #ifdef CONFIG_LOCKDEP 541 #define gpiochip_add_data(gc, data) ({ \ 542 static struct lock_class_key lock_key; \ 543 static struct lock_class_key request_key; \ 544 gpiochip_add_data_with_key(gc, data, &lock_key, \ 545 &request_key); \ 546 }) 547 #define devm_gpiochip_add_data(dev, gc, data) ({ \ 548 static struct lock_class_key lock_key; \ 549 static struct lock_class_key request_key; \ 550 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \ 551 &request_key); \ 552 }) 553 #else 554 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL) 555 #define devm_gpiochip_add_data(dev, gc, data) \ 556 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL) 557 #endif /* CONFIG_LOCKDEP */ 558 559 static inline int gpiochip_add(struct gpio_chip *gc) 560 { 561 return gpiochip_add_data(gc, NULL); 562 } 563 extern void gpiochip_remove(struct gpio_chip *gc); 564 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data, 565 struct lock_class_key *lock_key, 566 struct lock_class_key *request_key); 567 568 extern struct gpio_chip *gpiochip_find(void *data, 569 int (*match)(struct gpio_chip *gc, void *data)); 570 571 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset); 572 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset); 573 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset); 574 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset); 575 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); 576 577 /* Line status inquiry for drivers */ 578 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); 579 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); 580 581 /* Sleep persistence inquiry for drivers */ 582 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset); 583 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset); 584 585 /* get driver data */ 586 void *gpiochip_get_data(struct gpio_chip *gc); 587 588 struct bgpio_pdata { 589 const char *label; 590 int base; 591 int ngpio; 592 }; 593 594 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 595 596 void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, 597 unsigned int parent_hwirq, 598 unsigned int parent_type); 599 void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, 600 unsigned int parent_hwirq, 601 unsigned int parent_type); 602 603 #else 604 605 static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, 606 unsigned int parent_hwirq, 607 unsigned int parent_type) 608 { 609 return NULL; 610 } 611 612 static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, 613 unsigned int parent_hwirq, 614 unsigned int parent_type) 615 { 616 return NULL; 617 } 618 619 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ 620 621 int bgpio_init(struct gpio_chip *gc, struct device *dev, 622 unsigned long sz, void __iomem *dat, void __iomem *set, 623 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 624 unsigned long flags); 625 626 #define BGPIOF_BIG_ENDIAN BIT(0) 627 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 628 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 629 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 630 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 631 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 632 #define BGPIOF_NO_SET_ON_INPUT BIT(6) 633 634 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, 635 irq_hw_number_t hwirq); 636 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq); 637 638 int gpiochip_irq_domain_activate(struct irq_domain *domain, 639 struct irq_data *data, bool reserve); 640 void gpiochip_irq_domain_deactivate(struct irq_domain *domain, 641 struct irq_data *data); 642 643 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc, 644 unsigned int offset); 645 646 #ifdef CONFIG_GPIOLIB_IRQCHIP 647 int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 648 struct irq_domain *domain); 649 #else 650 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 651 struct irq_domain *domain) 652 { 653 WARN_ON(1); 654 return -EINVAL; 655 } 656 #endif 657 658 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset); 659 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset); 660 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset, 661 unsigned long config); 662 663 /** 664 * struct gpio_pin_range - pin range controlled by a gpio chip 665 * @node: list for maintaining set of pin ranges, used internally 666 * @pctldev: pinctrl device which handles corresponding pins 667 * @range: actual range of pins controlled by a gpio controller 668 */ 669 struct gpio_pin_range { 670 struct list_head node; 671 struct pinctrl_dev *pctldev; 672 struct pinctrl_gpio_range range; 673 }; 674 675 #ifdef CONFIG_PINCTRL 676 677 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 678 unsigned int gpio_offset, unsigned int pin_offset, 679 unsigned int npins); 680 int gpiochip_add_pingroup_range(struct gpio_chip *gc, 681 struct pinctrl_dev *pctldev, 682 unsigned int gpio_offset, const char *pin_group); 683 void gpiochip_remove_pin_ranges(struct gpio_chip *gc); 684 685 #else /* ! CONFIG_PINCTRL */ 686 687 static inline int 688 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 689 unsigned int gpio_offset, unsigned int pin_offset, 690 unsigned int npins) 691 { 692 return 0; 693 } 694 static inline int 695 gpiochip_add_pingroup_range(struct gpio_chip *gc, 696 struct pinctrl_dev *pctldev, 697 unsigned int gpio_offset, const char *pin_group) 698 { 699 return 0; 700 } 701 702 static inline void 703 gpiochip_remove_pin_ranges(struct gpio_chip *gc) 704 { 705 } 706 707 #endif /* CONFIG_PINCTRL */ 708 709 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc, 710 unsigned int hwnum, 711 const char *label, 712 enum gpio_lookup_flags lflags, 713 enum gpiod_flags dflags); 714 void gpiochip_free_own_desc(struct gpio_desc *desc); 715 716 #ifdef CONFIG_GPIOLIB 717 718 /* lock/unlock as IRQ */ 719 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset); 720 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset); 721 722 723 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 724 725 #else /* CONFIG_GPIOLIB */ 726 727 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 728 { 729 /* GPIO can never have been requested */ 730 WARN_ON(1); 731 return ERR_PTR(-ENODEV); 732 } 733 734 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc, 735 unsigned int offset) 736 { 737 WARN_ON(1); 738 return -EINVAL; 739 } 740 741 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc, 742 unsigned int offset) 743 { 744 WARN_ON(1); 745 } 746 #endif /* CONFIG_GPIOLIB */ 747 748 #endif /* __LINUX_GPIO_DRIVER_H */ 749