1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_GPIO_DRIVER_H 3 #define __LINUX_GPIO_DRIVER_H 4 5 #include <linux/device.h> 6 #include <linux/types.h> 7 #include <linux/irq.h> 8 #include <linux/irqchip/chained_irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/lockdep.h> 11 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 14 struct gpio_desc; 15 struct of_phandle_args; 16 struct device_node; 17 struct seq_file; 18 struct gpio_device; 19 struct module; 20 enum gpiod_flags; 21 enum gpio_lookup_flags; 22 23 struct gpio_chip; 24 25 /** 26 * struct gpio_irq_chip - GPIO interrupt controller 27 */ 28 struct gpio_irq_chip { 29 /** 30 * @chip: 31 * 32 * GPIO IRQ chip implementation, provided by GPIO driver. 33 */ 34 struct irq_chip *chip; 35 36 /** 37 * @domain: 38 * 39 * Interrupt translation domain; responsible for mapping between GPIO 40 * hwirq number and Linux IRQ number. 41 */ 42 struct irq_domain *domain; 43 44 /** 45 * @domain_ops: 46 * 47 * Table of interrupt domain operations for this IRQ chip. 48 */ 49 const struct irq_domain_ops *domain_ops; 50 51 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 52 /** 53 * @fwnode: 54 * 55 * Firmware node corresponding to this gpiochip/irqchip, necessary 56 * for hierarchical irqdomain support. 57 */ 58 struct fwnode_handle *fwnode; 59 60 /** 61 * @parent_domain: 62 * 63 * If non-NULL, will be set as the parent of this GPIO interrupt 64 * controller's IRQ domain to establish a hierarchical interrupt 65 * domain. The presence of this will activate the hierarchical 66 * interrupt support. 67 */ 68 struct irq_domain *parent_domain; 69 70 /** 71 * @child_to_parent_hwirq: 72 * 73 * This callback translates a child hardware IRQ offset to a parent 74 * hardware IRQ offset on a hierarchical interrupt chip. The child 75 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the 76 * ngpio field of struct gpio_chip) and the corresponding parent 77 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by 78 * the driver. The driver can calculate this from an offset or using 79 * a lookup table or whatever method is best for this chip. Return 80 * 0 on successful translation in the driver. 81 * 82 * If some ranges of hardware IRQs do not have a corresponding parent 83 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and 84 * @need_valid_mask to make these GPIO lines unavailable for 85 * translation. 86 */ 87 int (*child_to_parent_hwirq)(struct gpio_chip *chip, 88 unsigned int child_hwirq, 89 unsigned int child_type, 90 unsigned int *parent_hwirq, 91 unsigned int *parent_type); 92 93 /** 94 * @populate_parent_fwspec: 95 * 96 * This optional callback populates the &struct irq_fwspec for the 97 * parent's IRQ domain. If this is not specified, then 98 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell 99 * variant named &gpiochip_populate_parent_fwspec_fourcell is also 100 * available. 101 */ 102 void (*populate_parent_fwspec)(struct gpio_chip *chip, 103 struct irq_fwspec *fwspec, 104 unsigned int parent_hwirq, 105 unsigned int parent_type); 106 107 /** 108 * @child_offset_to_irq: 109 * 110 * This optional callback is used to translate the child's GPIO line 111 * offset on the GPIO chip to an IRQ number for the GPIO to_irq() 112 * callback. If this is not specified, then a default callback will be 113 * provided that returns the line offset. 114 */ 115 unsigned int (*child_offset_to_irq)(struct gpio_chip *chip, 116 unsigned int pin); 117 118 /** 119 * @child_irq_domain_ops: 120 * 121 * The IRQ domain operations that will be used for this GPIO IRQ 122 * chip. If no operations are provided, then default callbacks will 123 * be populated to setup the IRQ hierarchy. Some drivers need to 124 * supply their own translate function. 125 */ 126 struct irq_domain_ops child_irq_domain_ops; 127 #endif 128 129 /** 130 * @handler: 131 * 132 * The IRQ handler to use (often a predefined IRQ core function) for 133 * GPIO IRQs, provided by GPIO driver. 134 */ 135 irq_flow_handler_t handler; 136 137 /** 138 * @default_type: 139 * 140 * Default IRQ triggering type applied during GPIO driver 141 * initialization, provided by GPIO driver. 142 */ 143 unsigned int default_type; 144 145 /** 146 * @lock_key: 147 * 148 * Per GPIO IRQ chip lockdep class for IRQ lock. 149 */ 150 struct lock_class_key *lock_key; 151 152 /** 153 * @request_key: 154 * 155 * Per GPIO IRQ chip lockdep class for IRQ request. 156 */ 157 struct lock_class_key *request_key; 158 159 /** 160 * @parent_handler: 161 * 162 * The interrupt handler for the GPIO chip's parent interrupts, may be 163 * NULL if the parent interrupts are nested rather than cascaded. 164 */ 165 irq_flow_handler_t parent_handler; 166 167 /** 168 * @parent_handler_data: 169 * 170 * Data associated, and passed to, the handler for the parent 171 * interrupt. 172 */ 173 void *parent_handler_data; 174 175 /** 176 * @num_parents: 177 * 178 * The number of interrupt parents of a GPIO chip. 179 */ 180 unsigned int num_parents; 181 182 /** 183 * @parents: 184 * 185 * A list of interrupt parents of a GPIO chip. This is owned by the 186 * driver, so the core will only reference this list, not modify it. 187 */ 188 unsigned int *parents; 189 190 /** 191 * @map: 192 * 193 * A list of interrupt parents for each line of a GPIO chip. 194 */ 195 unsigned int *map; 196 197 /** 198 * @threaded: 199 * 200 * True if set the interrupt handling uses nested threads. 201 */ 202 bool threaded; 203 204 /** 205 * @init_valid_mask: optional routine to initialize @valid_mask, to be 206 * used if not all GPIO lines are valid interrupts. Sometimes some 207 * lines just cannot fire interrupts, and this routine, when defined, 208 * is passed a bitmap in "valid_mask" and it will have ngpios 209 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can 210 * then directly set some bits to "0" if they cannot be used for 211 * interrupts. 212 */ 213 void (*init_valid_mask)(struct gpio_chip *chip, 214 unsigned long *valid_mask, 215 unsigned int ngpios); 216 217 /** 218 * @valid_mask: 219 * 220 * If not %NULL holds bitmask of GPIOs which are valid to be included 221 * in IRQ domain of the chip. 222 */ 223 unsigned long *valid_mask; 224 225 /** 226 * @first: 227 * 228 * Required for static IRQ allocation. If set, irq_domain_add_simple() 229 * will allocate and map all IRQs during initialization. 230 */ 231 unsigned int first; 232 233 /** 234 * @irq_enable: 235 * 236 * Store old irq_chip irq_enable callback 237 */ 238 void (*irq_enable)(struct irq_data *data); 239 240 /** 241 * @irq_disable: 242 * 243 * Store old irq_chip irq_disable callback 244 */ 245 void (*irq_disable)(struct irq_data *data); 246 }; 247 248 /** 249 * struct gpio_chip - abstract a GPIO controller 250 * @label: a functional name for the GPIO device, such as a part 251 * number or the name of the SoC IP-block implementing it. 252 * @gpiodev: the internal state holder, opaque struct 253 * @parent: optional parent device providing the GPIOs 254 * @owner: helps prevent removal of modules exporting active GPIOs 255 * @request: optional hook for chip-specific activation, such as 256 * enabling module power and clock; may sleep 257 * @free: optional hook for chip-specific deactivation, such as 258 * disabling module power and clock; may sleep 259 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 260 * (same as GPIOF_DIR_XXX), or negative error. 261 * It is recommended to always implement this function, even on 262 * input-only or output-only gpio chips. 263 * @direction_input: configures signal "offset" as input, or returns error 264 * This can be omitted on input-only or output-only gpio chips. 265 * @direction_output: configures signal "offset" as output, or returns error 266 * This can be omitted on input-only or output-only gpio chips. 267 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 268 * @get_multiple: reads values for multiple signals defined by "mask" and 269 * stores them in "bits", returns 0 on success or negative error 270 * @set: assigns output value for signal "offset" 271 * @set_multiple: assigns output values for multiple signals defined by "mask" 272 * @set_config: optional hook for all kinds of settings. Uses the same 273 * packed config format as generic pinconf. 274 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings; 275 * implementation may not sleep 276 * @dbg_show: optional routine to show contents in debugfs; default code 277 * will be used when this is omitted, but custom code can show extra 278 * state (such as pullup/pulldown configuration). 279 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if 280 * not all GPIOs are valid. 281 * @base: identifies the first GPIO number handled by this chip; 282 * or, if negative during registration, requests dynamic ID allocation. 283 * DEPRECATION: providing anything non-negative and nailing the base 284 * offset of GPIO chips is deprecated. Please pass -1 as base to 285 * let gpiolib select the chip base in all possible cases. We want to 286 * get rid of the static GPIO number space in the long run. 287 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 288 * handled is (base + ngpio - 1). 289 * @names: if set, must be an array of strings to use as alternative 290 * names for the GPIOs in this chip. Any entry in the array 291 * may be NULL if there is no alias for the GPIO, however the 292 * array must be @ngpio entries long. A name can include a single printk 293 * format specifier for an unsigned int. It is substituted by the actual 294 * number of the gpio. 295 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 296 * must while accessing GPIO expander chips over I2C or SPI. This 297 * implies that if the chip supports IRQs, these IRQs need to be threaded 298 * as the chip access may sleep when e.g. reading out the IRQ status 299 * registers. 300 * @read_reg: reader function for generic GPIO 301 * @write_reg: writer function for generic GPIO 302 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing 303 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the 304 * generic GPIO core. It is for internal housekeeping only. 305 * @reg_dat: data (in) register for generic GPIO 306 * @reg_set: output set register (out=high) for generic GPIO 307 * @reg_clr: output clear register (out=low) for generic GPIO 308 * @reg_dir_out: direction out setting register for generic GPIO 309 * @reg_dir_in: direction in setting register for generic GPIO 310 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 311 * be read and we need to rely on out internal state tracking. 312 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 313 * <register width> * 8 314 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 315 * shadowed and real data registers writes together. 316 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 317 * safely. 318 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 319 * direction safely. A "1" in this word means the line is set as 320 * output. 321 * 322 * A gpio_chip can help platforms abstract various sources of GPIOs so 323 * they can all be accessed through a common programing interface. 324 * Example sources would be SOC controllers, FPGAs, multifunction 325 * chips, dedicated GPIO expanders, and so on. 326 * 327 * Each chip controls a number of signals, identified in method calls 328 * by "offset" values in the range 0..(@ngpio - 1). When those signals 329 * are referenced through calls like gpio_get_value(gpio), the offset 330 * is calculated by subtracting @base from the gpio number. 331 */ 332 struct gpio_chip { 333 const char *label; 334 struct gpio_device *gpiodev; 335 struct device *parent; 336 struct module *owner; 337 338 int (*request)(struct gpio_chip *chip, 339 unsigned offset); 340 void (*free)(struct gpio_chip *chip, 341 unsigned offset); 342 int (*get_direction)(struct gpio_chip *chip, 343 unsigned offset); 344 int (*direction_input)(struct gpio_chip *chip, 345 unsigned offset); 346 int (*direction_output)(struct gpio_chip *chip, 347 unsigned offset, int value); 348 int (*get)(struct gpio_chip *chip, 349 unsigned offset); 350 int (*get_multiple)(struct gpio_chip *chip, 351 unsigned long *mask, 352 unsigned long *bits); 353 void (*set)(struct gpio_chip *chip, 354 unsigned offset, int value); 355 void (*set_multiple)(struct gpio_chip *chip, 356 unsigned long *mask, 357 unsigned long *bits); 358 int (*set_config)(struct gpio_chip *chip, 359 unsigned offset, 360 unsigned long config); 361 int (*to_irq)(struct gpio_chip *chip, 362 unsigned offset); 363 364 void (*dbg_show)(struct seq_file *s, 365 struct gpio_chip *chip); 366 367 int (*init_valid_mask)(struct gpio_chip *chip, 368 unsigned long *valid_mask, 369 unsigned int ngpios); 370 371 int base; 372 u16 ngpio; 373 const char *const *names; 374 bool can_sleep; 375 376 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 377 unsigned long (*read_reg)(void __iomem *reg); 378 void (*write_reg)(void __iomem *reg, unsigned long data); 379 bool be_bits; 380 void __iomem *reg_dat; 381 void __iomem *reg_set; 382 void __iomem *reg_clr; 383 void __iomem *reg_dir_out; 384 void __iomem *reg_dir_in; 385 bool bgpio_dir_unreadable; 386 int bgpio_bits; 387 spinlock_t bgpio_lock; 388 unsigned long bgpio_data; 389 unsigned long bgpio_dir; 390 #endif /* CONFIG_GPIO_GENERIC */ 391 392 #ifdef CONFIG_GPIOLIB_IRQCHIP 393 /* 394 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 395 * to handle IRQs for most practical cases. 396 */ 397 398 /** 399 * @irq: 400 * 401 * Integrates interrupt chip functionality with the GPIO chip. Can be 402 * used to handle IRQs for most practical cases. 403 */ 404 struct gpio_irq_chip irq; 405 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 406 407 /** 408 * @valid_mask: 409 * 410 * If not %NULL holds bitmask of GPIOs which are valid to be used 411 * from the chip. 412 */ 413 unsigned long *valid_mask; 414 415 #if defined(CONFIG_OF_GPIO) 416 /* 417 * If CONFIG_OF is enabled, then all GPIO controllers described in the 418 * device tree automatically may have an OF translation 419 */ 420 421 /** 422 * @of_node: 423 * 424 * Pointer to a device tree node representing this GPIO controller. 425 */ 426 struct device_node *of_node; 427 428 /** 429 * @of_gpio_n_cells: 430 * 431 * Number of cells used to form the GPIO specifier. 432 */ 433 unsigned int of_gpio_n_cells; 434 435 /** 436 * @of_xlate: 437 * 438 * Callback to translate a device tree GPIO specifier into a chip- 439 * relative GPIO number and flags. 440 */ 441 int (*of_xlate)(struct gpio_chip *gc, 442 const struct of_phandle_args *gpiospec, u32 *flags); 443 #endif /* CONFIG_OF_GPIO */ 444 }; 445 446 extern const char *gpiochip_is_requested(struct gpio_chip *chip, 447 unsigned offset); 448 449 /* add/remove chips */ 450 extern int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data, 451 struct lock_class_key *lock_key, 452 struct lock_class_key *request_key); 453 454 /** 455 * gpiochip_add_data() - register a gpio_chip 456 * @chip: the chip to register, with chip->base initialized 457 * @data: driver-private data associated with this chip 458 * 459 * Context: potentially before irqs will work 460 * 461 * When gpiochip_add_data() is called very early during boot, so that GPIOs 462 * can be freely used, the chip->parent device must be registered before 463 * the gpio framework's arch_initcall(). Otherwise sysfs initialization 464 * for GPIOs will fail rudely. 465 * 466 * gpiochip_add_data() must only be called after gpiolib initialization, 467 * ie after core_initcall(). 468 * 469 * If chip->base is negative, this requests dynamic assignment of 470 * a range of valid GPIOs. 471 * 472 * Returns: 473 * A negative errno if the chip can't be registered, such as because the 474 * chip->base is invalid or already associated with a different chip. 475 * Otherwise it returns zero as a success code. 476 */ 477 #ifdef CONFIG_LOCKDEP 478 #define gpiochip_add_data(chip, data) ({ \ 479 static struct lock_class_key lock_key; \ 480 static struct lock_class_key request_key; \ 481 gpiochip_add_data_with_key(chip, data, &lock_key, \ 482 &request_key); \ 483 }) 484 #else 485 #define gpiochip_add_data(chip, data) gpiochip_add_data_with_key(chip, data, NULL, NULL) 486 #endif /* CONFIG_LOCKDEP */ 487 488 static inline int gpiochip_add(struct gpio_chip *chip) 489 { 490 return gpiochip_add_data(chip, NULL); 491 } 492 extern void gpiochip_remove(struct gpio_chip *chip); 493 extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip, 494 void *data); 495 496 extern struct gpio_chip *gpiochip_find(void *data, 497 int (*match)(struct gpio_chip *chip, void *data)); 498 499 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset); 500 int gpiochip_reqres_irq(struct gpio_chip *chip, unsigned int offset); 501 void gpiochip_relres_irq(struct gpio_chip *chip, unsigned int offset); 502 void gpiochip_disable_irq(struct gpio_chip *chip, unsigned int offset); 503 void gpiochip_enable_irq(struct gpio_chip *chip, unsigned int offset); 504 505 /* Line status inquiry for drivers */ 506 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset); 507 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset); 508 509 /* Sleep persistence inquiry for drivers */ 510 bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset); 511 bool gpiochip_line_is_valid(const struct gpio_chip *chip, unsigned int offset); 512 513 /* get driver data */ 514 void *gpiochip_get_data(struct gpio_chip *chip); 515 516 struct bgpio_pdata { 517 const char *label; 518 int base; 519 int ngpio; 520 }; 521 522 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 523 524 void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chip, 525 struct irq_fwspec *fwspec, 526 unsigned int parent_hwirq, 527 unsigned int parent_type); 528 void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip, 529 struct irq_fwspec *fwspec, 530 unsigned int parent_hwirq, 531 unsigned int parent_type); 532 533 #else 534 535 static inline void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chip, 536 struct irq_fwspec *fwspec, 537 unsigned int parent_hwirq, 538 unsigned int parent_type) 539 { 540 } 541 542 static inline void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip, 543 struct irq_fwspec *fwspec, 544 unsigned int parent_hwirq, 545 unsigned int parent_type) 546 { 547 } 548 549 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ 550 551 int bgpio_init(struct gpio_chip *gc, struct device *dev, 552 unsigned long sz, void __iomem *dat, void __iomem *set, 553 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 554 unsigned long flags); 555 556 #define BGPIOF_BIG_ENDIAN BIT(0) 557 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 558 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 559 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 560 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 561 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 562 563 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, 564 irq_hw_number_t hwirq); 565 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq); 566 567 int gpiochip_irq_domain_activate(struct irq_domain *domain, 568 struct irq_data *data, bool reserve); 569 void gpiochip_irq_domain_deactivate(struct irq_domain *domain, 570 struct irq_data *data); 571 572 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip, 573 struct irq_chip *irqchip, 574 unsigned int parent_irq, 575 irq_flow_handler_t parent_handler); 576 577 void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip, 578 struct irq_chip *irqchip, 579 unsigned int parent_irq); 580 581 int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip, 582 struct irq_chip *irqchip, 583 unsigned int first_irq, 584 irq_flow_handler_t handler, 585 unsigned int type, 586 bool threaded, 587 struct lock_class_key *lock_key, 588 struct lock_class_key *request_key); 589 590 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip, 591 unsigned int offset); 592 593 #ifdef CONFIG_LOCKDEP 594 595 /* 596 * Lockdep requires that each irqchip instance be created with a 597 * unique key so as to avoid unnecessary warnings. This upfront 598 * boilerplate static inlines provides such a key for each 599 * unique instance. 600 */ 601 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip, 602 struct irq_chip *irqchip, 603 unsigned int first_irq, 604 irq_flow_handler_t handler, 605 unsigned int type) 606 { 607 static struct lock_class_key lock_key; 608 static struct lock_class_key request_key; 609 610 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, 611 handler, type, false, 612 &lock_key, &request_key); 613 } 614 615 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip, 616 struct irq_chip *irqchip, 617 unsigned int first_irq, 618 irq_flow_handler_t handler, 619 unsigned int type) 620 { 621 622 static struct lock_class_key lock_key; 623 static struct lock_class_key request_key; 624 625 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, 626 handler, type, true, 627 &lock_key, &request_key); 628 } 629 #else /* ! CONFIG_LOCKDEP */ 630 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip, 631 struct irq_chip *irqchip, 632 unsigned int first_irq, 633 irq_flow_handler_t handler, 634 unsigned int type) 635 { 636 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, 637 handler, type, false, NULL, NULL); 638 } 639 640 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip, 641 struct irq_chip *irqchip, 642 unsigned int first_irq, 643 irq_flow_handler_t handler, 644 unsigned int type) 645 { 646 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq, 647 handler, type, true, NULL, NULL); 648 } 649 #endif /* CONFIG_LOCKDEP */ 650 651 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset); 652 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset); 653 int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset, 654 unsigned long config); 655 656 /** 657 * struct gpio_pin_range - pin range controlled by a gpio chip 658 * @node: list for maintaining set of pin ranges, used internally 659 * @pctldev: pinctrl device which handles corresponding pins 660 * @range: actual range of pins controlled by a gpio controller 661 */ 662 struct gpio_pin_range { 663 struct list_head node; 664 struct pinctrl_dev *pctldev; 665 struct pinctrl_gpio_range range; 666 }; 667 668 #ifdef CONFIG_PINCTRL 669 670 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, 671 unsigned int gpio_offset, unsigned int pin_offset, 672 unsigned int npins); 673 int gpiochip_add_pingroup_range(struct gpio_chip *chip, 674 struct pinctrl_dev *pctldev, 675 unsigned int gpio_offset, const char *pin_group); 676 void gpiochip_remove_pin_ranges(struct gpio_chip *chip); 677 678 #else /* ! CONFIG_PINCTRL */ 679 680 static inline int 681 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, 682 unsigned int gpio_offset, unsigned int pin_offset, 683 unsigned int npins) 684 { 685 return 0; 686 } 687 static inline int 688 gpiochip_add_pingroup_range(struct gpio_chip *chip, 689 struct pinctrl_dev *pctldev, 690 unsigned int gpio_offset, const char *pin_group) 691 { 692 return 0; 693 } 694 695 static inline void 696 gpiochip_remove_pin_ranges(struct gpio_chip *chip) 697 { 698 } 699 700 #endif /* CONFIG_PINCTRL */ 701 702 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum, 703 const char *label, 704 enum gpio_lookup_flags lflags, 705 enum gpiod_flags dflags); 706 void gpiochip_free_own_desc(struct gpio_desc *desc); 707 708 void devprop_gpiochip_set_names(struct gpio_chip *chip, 709 const struct fwnode_handle *fwnode); 710 711 #ifdef CONFIG_GPIOLIB 712 713 /* lock/unlock as IRQ */ 714 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset); 715 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset); 716 717 718 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 719 720 #else /* CONFIG_GPIOLIB */ 721 722 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 723 { 724 /* GPIO can never have been requested */ 725 WARN_ON(1); 726 return ERR_PTR(-ENODEV); 727 } 728 729 static inline int gpiochip_lock_as_irq(struct gpio_chip *chip, 730 unsigned int offset) 731 { 732 WARN_ON(1); 733 return -EINVAL; 734 } 735 736 static inline void gpiochip_unlock_as_irq(struct gpio_chip *chip, 737 unsigned int offset) 738 { 739 WARN_ON(1); 740 } 741 #endif /* CONFIG_GPIOLIB */ 742 743 #endif /* __LINUX_GPIO_DRIVER_H */ 744