xref: /openbmc/linux/include/linux/gpio/driver.h (revision 827634ad)
1 #ifndef __LINUX_GPIO_DRIVER_H
2 #define __LINUX_GPIO_DRIVER_H
3 
4 #include <linux/types.h>
5 #include <linux/module.h>
6 #include <linux/irq.h>
7 #include <linux/irqchip/chained_irq.h>
8 #include <linux/irqdomain.h>
9 #include <linux/pinctrl/pinctrl.h>
10 
11 struct device;
12 struct gpio_desc;
13 struct of_phandle_args;
14 struct device_node;
15 struct seq_file;
16 
17 #ifdef CONFIG_GPIOLIB
18 
19 /**
20  * struct gpio_chip - abstract a GPIO controller
21  * @label: for diagnostics
22  * @dev: optional device providing the GPIOs
23  * @owner: helps prevent removal of modules exporting active GPIOs
24  * @list: links gpio_chips together for traversal
25  * @request: optional hook for chip-specific activation, such as
26  *	enabling module power and clock; may sleep
27  * @free: optional hook for chip-specific deactivation, such as
28  *	disabling module power and clock; may sleep
29  * @get_direction: returns direction for signal "offset", 0=out, 1=in,
30  *	(same as GPIOF_DIR_XXX), or negative error
31  * @direction_input: configures signal "offset" as input, or returns error
32  * @direction_output: configures signal "offset" as output, or returns error
33  * @get: returns value for signal "offset"; for output signals this
34  *	returns either the value actually sensed, or zero
35  * @set: assigns output value for signal "offset"
36  * @set_multiple: assigns output values for multiple signals defined by "mask"
37  * @set_debounce: optional hook for setting debounce time for specified gpio in
38  *      interrupt triggered gpio chips
39  * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
40  *	implementation may not sleep
41  * @dbg_show: optional routine to show contents in debugfs; default code
42  *	will be used when this is omitted, but custom code can show extra
43  *	state (such as pullup/pulldown configuration).
44  * @base: identifies the first GPIO number handled by this chip; or, if
45  *	negative during registration, requests dynamic ID allocation.
46  * @ngpio: the number of GPIOs handled by this controller; the last GPIO
47  *	handled is (base + ngpio - 1).
48  * @desc: array of ngpio descriptors. Private.
49  * @names: if set, must be an array of strings to use as alternative
50  *      names for the GPIOs in this chip. Any entry in the array
51  *      may be NULL if there is no alias for the GPIO, however the
52  *      array must be @ngpio entries long.  A name can include a single printk
53  *      format specifier for an unsigned int.  It is substituted by the actual
54  *      number of the gpio.
55  * @can_sleep: flag must be set iff get()/set() methods sleep, as they
56  *	must while accessing GPIO expander chips over I2C or SPI. This
57  *	implies that if the chip supports IRQs, these IRQs need to be threaded
58  *	as the chip access may sleep when e.g. reading out the IRQ status
59  *	registers.
60  * @exported: flags if the gpiochip is exported for use from sysfs. Private.
61  * @irq_not_threaded: flag must be set if @can_sleep is set but the
62  *	IRQs don't need to be threaded
63  *
64  * A gpio_chip can help platforms abstract various sources of GPIOs so
65  * they can all be accessed through a common programing interface.
66  * Example sources would be SOC controllers, FPGAs, multifunction
67  * chips, dedicated GPIO expanders, and so on.
68  *
69  * Each chip controls a number of signals, identified in method calls
70  * by "offset" values in the range 0..(@ngpio - 1).  When those signals
71  * are referenced through calls like gpio_get_value(gpio), the offset
72  * is calculated by subtracting @base from the gpio number.
73  */
74 struct gpio_chip {
75 	const char		*label;
76 	struct device		*dev;
77 	struct module		*owner;
78 	struct list_head        list;
79 
80 	int			(*request)(struct gpio_chip *chip,
81 						unsigned offset);
82 	void			(*free)(struct gpio_chip *chip,
83 						unsigned offset);
84 	int			(*get_direction)(struct gpio_chip *chip,
85 						unsigned offset);
86 	int			(*direction_input)(struct gpio_chip *chip,
87 						unsigned offset);
88 	int			(*direction_output)(struct gpio_chip *chip,
89 						unsigned offset, int value);
90 	int			(*get)(struct gpio_chip *chip,
91 						unsigned offset);
92 	void			(*set)(struct gpio_chip *chip,
93 						unsigned offset, int value);
94 	void			(*set_multiple)(struct gpio_chip *chip,
95 						unsigned long *mask,
96 						unsigned long *bits);
97 	int			(*set_debounce)(struct gpio_chip *chip,
98 						unsigned offset,
99 						unsigned debounce);
100 
101 	int			(*to_irq)(struct gpio_chip *chip,
102 						unsigned offset);
103 
104 	void			(*dbg_show)(struct seq_file *s,
105 						struct gpio_chip *chip);
106 	int			base;
107 	u16			ngpio;
108 	struct gpio_desc	*desc;
109 	const char		*const *names;
110 	bool			can_sleep;
111 	bool			irq_not_threaded;
112 	bool			exported;
113 
114 #ifdef CONFIG_GPIOLIB_IRQCHIP
115 	/*
116 	 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
117 	 * to handle IRQs for most practical cases.
118 	 */
119 	struct irq_chip		*irqchip;
120 	struct irq_domain	*irqdomain;
121 	unsigned int		irq_base;
122 	irq_flow_handler_t	irq_handler;
123 	unsigned int		irq_default_type;
124 #endif
125 
126 #if defined(CONFIG_OF_GPIO)
127 	/*
128 	 * If CONFIG_OF is enabled, then all GPIO controllers described in the
129 	 * device tree automatically may have an OF translation
130 	 */
131 	struct device_node *of_node;
132 	int of_gpio_n_cells;
133 	int (*of_xlate)(struct gpio_chip *gc,
134 			const struct of_phandle_args *gpiospec, u32 *flags);
135 #endif
136 #ifdef CONFIG_PINCTRL
137 	/*
138 	 * If CONFIG_PINCTRL is enabled, then gpio controllers can optionally
139 	 * describe the actual pin range which they serve in an SoC. This
140 	 * information would be used by pinctrl subsystem to configure
141 	 * corresponding pins for gpio usage.
142 	 */
143 	struct list_head pin_ranges;
144 #endif
145 };
146 
147 extern const char *gpiochip_is_requested(struct gpio_chip *chip,
148 			unsigned offset);
149 
150 /* add/remove chips */
151 extern int gpiochip_add(struct gpio_chip *chip);
152 extern void gpiochip_remove(struct gpio_chip *chip);
153 extern struct gpio_chip *gpiochip_find(void *data,
154 			      int (*match)(struct gpio_chip *chip, void *data));
155 
156 /* lock/unlock as IRQ */
157 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
158 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
159 
160 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
161 
162 #ifdef CONFIG_GPIOLIB_IRQCHIP
163 
164 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
165 		struct irq_chip *irqchip,
166 		int parent_irq,
167 		irq_flow_handler_t parent_handler);
168 
169 int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
170 		struct irq_chip *irqchip,
171 		unsigned int first_irq,
172 		irq_flow_handler_t handler,
173 		unsigned int type);
174 
175 #endif /* CONFIG_GPIOLIB_IRQCHIP */
176 
177 #ifdef CONFIG_PINCTRL
178 
179 /**
180  * struct gpio_pin_range - pin range controlled by a gpio chip
181  * @head: list for maintaining set of pin ranges, used internally
182  * @pctldev: pinctrl device which handles corresponding pins
183  * @range: actual range of pins controlled by a gpio controller
184  */
185 
186 struct gpio_pin_range {
187 	struct list_head node;
188 	struct pinctrl_dev *pctldev;
189 	struct pinctrl_gpio_range range;
190 };
191 
192 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
193 			   unsigned int gpio_offset, unsigned int pin_offset,
194 			   unsigned int npins);
195 int gpiochip_add_pingroup_range(struct gpio_chip *chip,
196 			struct pinctrl_dev *pctldev,
197 			unsigned int gpio_offset, const char *pin_group);
198 void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
199 
200 #else
201 
202 static inline int
203 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
204 		       unsigned int gpio_offset, unsigned int pin_offset,
205 		       unsigned int npins)
206 {
207 	return 0;
208 }
209 static inline int
210 gpiochip_add_pingroup_range(struct gpio_chip *chip,
211 			struct pinctrl_dev *pctldev,
212 			unsigned int gpio_offset, const char *pin_group)
213 {
214 	return 0;
215 }
216 
217 static inline void
218 gpiochip_remove_pin_ranges(struct gpio_chip *chip)
219 {
220 }
221 
222 #endif /* CONFIG_PINCTRL */
223 
224 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
225 					    const char *label);
226 void gpiochip_free_own_desc(struct gpio_desc *desc);
227 
228 #else /* CONFIG_GPIOLIB */
229 
230 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
231 {
232 	/* GPIO can never have been requested */
233 	WARN_ON(1);
234 	return ERR_PTR(-ENODEV);
235 }
236 
237 #endif /* CONFIG_GPIOLIB */
238 
239 #endif
240