1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_GPIO_DRIVER_H 3 #define __LINUX_GPIO_DRIVER_H 4 5 #include <linux/device.h> 6 #include <linux/types.h> 7 #include <linux/irq.h> 8 #include <linux/irqchip/chained_irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/lockdep.h> 11 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 14 struct gpio_desc; 15 struct of_phandle_args; 16 struct device_node; 17 struct seq_file; 18 struct gpio_device; 19 struct module; 20 enum gpiod_flags; 21 enum gpio_lookup_flags; 22 23 struct gpio_chip; 24 25 #define GPIO_LINE_DIRECTION_IN 1 26 #define GPIO_LINE_DIRECTION_OUT 0 27 28 /** 29 * struct gpio_irq_chip - GPIO interrupt controller 30 */ 31 struct gpio_irq_chip { 32 /** 33 * @chip: 34 * 35 * GPIO IRQ chip implementation, provided by GPIO driver. 36 */ 37 struct irq_chip *chip; 38 39 /** 40 * @domain: 41 * 42 * Interrupt translation domain; responsible for mapping between GPIO 43 * hwirq number and Linux IRQ number. 44 */ 45 struct irq_domain *domain; 46 47 /** 48 * @domain_ops: 49 * 50 * Table of interrupt domain operations for this IRQ chip. 51 */ 52 const struct irq_domain_ops *domain_ops; 53 54 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 55 /** 56 * @fwnode: 57 * 58 * Firmware node corresponding to this gpiochip/irqchip, necessary 59 * for hierarchical irqdomain support. 60 */ 61 struct fwnode_handle *fwnode; 62 63 /** 64 * @parent_domain: 65 * 66 * If non-NULL, will be set as the parent of this GPIO interrupt 67 * controller's IRQ domain to establish a hierarchical interrupt 68 * domain. The presence of this will activate the hierarchical 69 * interrupt support. 70 */ 71 struct irq_domain *parent_domain; 72 73 /** 74 * @child_to_parent_hwirq: 75 * 76 * This callback translates a child hardware IRQ offset to a parent 77 * hardware IRQ offset on a hierarchical interrupt chip. The child 78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the 79 * ngpio field of struct gpio_chip) and the corresponding parent 80 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by 81 * the driver. The driver can calculate this from an offset or using 82 * a lookup table or whatever method is best for this chip. Return 83 * 0 on successful translation in the driver. 84 * 85 * If some ranges of hardware IRQs do not have a corresponding parent 86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and 87 * @need_valid_mask to make these GPIO lines unavailable for 88 * translation. 89 */ 90 int (*child_to_parent_hwirq)(struct gpio_chip *gc, 91 unsigned int child_hwirq, 92 unsigned int child_type, 93 unsigned int *parent_hwirq, 94 unsigned int *parent_type); 95 96 /** 97 * @populate_parent_alloc_arg : 98 * 99 * This optional callback allocates and populates the specific struct 100 * for the parent's IRQ domain. If this is not specified, then 101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell 102 * variant named &gpiochip_populate_parent_fwspec_fourcell is also 103 * available. 104 */ 105 void *(*populate_parent_alloc_arg)(struct gpio_chip *gc, 106 unsigned int parent_hwirq, 107 unsigned int parent_type); 108 109 /** 110 * @child_offset_to_irq: 111 * 112 * This optional callback is used to translate the child's GPIO line 113 * offset on the GPIO chip to an IRQ number for the GPIO to_irq() 114 * callback. If this is not specified, then a default callback will be 115 * provided that returns the line offset. 116 */ 117 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc, 118 unsigned int pin); 119 120 /** 121 * @child_irq_domain_ops: 122 * 123 * The IRQ domain operations that will be used for this GPIO IRQ 124 * chip. If no operations are provided, then default callbacks will 125 * be populated to setup the IRQ hierarchy. Some drivers need to 126 * supply their own translate function. 127 */ 128 struct irq_domain_ops child_irq_domain_ops; 129 #endif 130 131 /** 132 * @handler: 133 * 134 * The IRQ handler to use (often a predefined IRQ core function) for 135 * GPIO IRQs, provided by GPIO driver. 136 */ 137 irq_flow_handler_t handler; 138 139 /** 140 * @default_type: 141 * 142 * Default IRQ triggering type applied during GPIO driver 143 * initialization, provided by GPIO driver. 144 */ 145 unsigned int default_type; 146 147 /** 148 * @lock_key: 149 * 150 * Per GPIO IRQ chip lockdep class for IRQ lock. 151 */ 152 struct lock_class_key *lock_key; 153 154 /** 155 * @request_key: 156 * 157 * Per GPIO IRQ chip lockdep class for IRQ request. 158 */ 159 struct lock_class_key *request_key; 160 161 /** 162 * @parent_handler: 163 * 164 * The interrupt handler for the GPIO chip's parent interrupts, may be 165 * NULL if the parent interrupts are nested rather than cascaded. 166 */ 167 irq_flow_handler_t parent_handler; 168 169 /** 170 * @parent_handler_data: 171 * @parent_handler_data_array: 172 * 173 * Data associated, and passed to, the handler for the parent 174 * interrupt. Can either be a single pointer if @per_parent_data 175 * is false, or an array of @num_parents pointers otherwise. If 176 * @per_parent_data is true, @parent_handler_data_array cannot be 177 * NULL. 178 */ 179 union { 180 void *parent_handler_data; 181 void **parent_handler_data_array; 182 }; 183 184 /** 185 * @num_parents: 186 * 187 * The number of interrupt parents of a GPIO chip. 188 */ 189 unsigned int num_parents; 190 191 /** 192 * @parents: 193 * 194 * A list of interrupt parents of a GPIO chip. This is owned by the 195 * driver, so the core will only reference this list, not modify it. 196 */ 197 unsigned int *parents; 198 199 /** 200 * @map: 201 * 202 * A list of interrupt parents for each line of a GPIO chip. 203 */ 204 unsigned int *map; 205 206 /** 207 * @threaded: 208 * 209 * True if set the interrupt handling uses nested threads. 210 */ 211 bool threaded; 212 213 /** 214 * @per_parent_data: 215 * 216 * True if parent_handler_data_array describes a @num_parents 217 * sized array to be used as parent data. 218 */ 219 bool per_parent_data; 220 221 /** 222 * @init_hw: optional routine to initialize hardware before 223 * an IRQ chip will be added. This is quite useful when 224 * a particular driver wants to clear IRQ related registers 225 * in order to avoid undesired events. 226 */ 227 int (*init_hw)(struct gpio_chip *gc); 228 229 /** 230 * @init_valid_mask: optional routine to initialize @valid_mask, to be 231 * used if not all GPIO lines are valid interrupts. Sometimes some 232 * lines just cannot fire interrupts, and this routine, when defined, 233 * is passed a bitmap in "valid_mask" and it will have ngpios 234 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can 235 * then directly set some bits to "0" if they cannot be used for 236 * interrupts. 237 */ 238 void (*init_valid_mask)(struct gpio_chip *gc, 239 unsigned long *valid_mask, 240 unsigned int ngpios); 241 242 /** 243 * @valid_mask: 244 * 245 * If not %NULL, holds bitmask of GPIOs which are valid to be included 246 * in IRQ domain of the chip. 247 */ 248 unsigned long *valid_mask; 249 250 /** 251 * @first: 252 * 253 * Required for static IRQ allocation. If set, irq_domain_add_simple() 254 * will allocate and map all IRQs during initialization. 255 */ 256 unsigned int first; 257 258 /** 259 * @irq_enable: 260 * 261 * Store old irq_chip irq_enable callback 262 */ 263 void (*irq_enable)(struct irq_data *data); 264 265 /** 266 * @irq_disable: 267 * 268 * Store old irq_chip irq_disable callback 269 */ 270 void (*irq_disable)(struct irq_data *data); 271 /** 272 * @irq_unmask: 273 * 274 * Store old irq_chip irq_unmask callback 275 */ 276 void (*irq_unmask)(struct irq_data *data); 277 278 /** 279 * @irq_mask: 280 * 281 * Store old irq_chip irq_mask callback 282 */ 283 void (*irq_mask)(struct irq_data *data); 284 }; 285 286 /** 287 * struct gpio_chip - abstract a GPIO controller 288 * @label: a functional name for the GPIO device, such as a part 289 * number or the name of the SoC IP-block implementing it. 290 * @gpiodev: the internal state holder, opaque struct 291 * @parent: optional parent device providing the GPIOs 292 * @fwnode: optional fwnode providing this controller's properties 293 * @owner: helps prevent removal of modules exporting active GPIOs 294 * @request: optional hook for chip-specific activation, such as 295 * enabling module power and clock; may sleep 296 * @free: optional hook for chip-specific deactivation, such as 297 * disabling module power and clock; may sleep 298 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 299 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN), 300 * or negative error. It is recommended to always implement this 301 * function, even on input-only or output-only gpio chips. 302 * @direction_input: configures signal "offset" as input, or returns error 303 * This can be omitted on input-only or output-only gpio chips. 304 * @direction_output: configures signal "offset" as output, or returns error 305 * This can be omitted on input-only or output-only gpio chips. 306 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 307 * @get_multiple: reads values for multiple signals defined by "mask" and 308 * stores them in "bits", returns 0 on success or negative error 309 * @set: assigns output value for signal "offset" 310 * @set_multiple: assigns output values for multiple signals defined by "mask" 311 * @set_config: optional hook for all kinds of settings. Uses the same 312 * packed config format as generic pinconf. 313 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings; 314 * implementation may not sleep 315 * @dbg_show: optional routine to show contents in debugfs; default code 316 * will be used when this is omitted, but custom code can show extra 317 * state (such as pullup/pulldown configuration). 318 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if 319 * not all GPIOs are valid. 320 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when 321 * requires special mapping of the pins that provides GPIO functionality. 322 * It is called after adding GPIO chip and before adding IRQ chip. 323 * @base: identifies the first GPIO number handled by this chip; 324 * or, if negative during registration, requests dynamic ID allocation. 325 * DEPRECATION: providing anything non-negative and nailing the base 326 * offset of GPIO chips is deprecated. Please pass -1 as base to 327 * let gpiolib select the chip base in all possible cases. We want to 328 * get rid of the static GPIO number space in the long run. 329 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 330 * handled is (base + ngpio - 1). 331 * @offset: when multiple gpio chips belong to the same device this 332 * can be used as offset within the device so friendly names can 333 * be properly assigned. 334 * @names: if set, must be an array of strings to use as alternative 335 * names for the GPIOs in this chip. Any entry in the array 336 * may be NULL if there is no alias for the GPIO, however the 337 * array must be @ngpio entries long. A name can include a single printk 338 * format specifier for an unsigned int. It is substituted by the actual 339 * number of the gpio. 340 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 341 * must while accessing GPIO expander chips over I2C or SPI. This 342 * implies that if the chip supports IRQs, these IRQs need to be threaded 343 * as the chip access may sleep when e.g. reading out the IRQ status 344 * registers. 345 * @read_reg: reader function for generic GPIO 346 * @write_reg: writer function for generic GPIO 347 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing 348 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the 349 * generic GPIO core. It is for internal housekeeping only. 350 * @reg_dat: data (in) register for generic GPIO 351 * @reg_set: output set register (out=high) for generic GPIO 352 * @reg_clr: output clear register (out=low) for generic GPIO 353 * @reg_dir_out: direction out setting register for generic GPIO 354 * @reg_dir_in: direction in setting register for generic GPIO 355 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 356 * be read and we need to rely on out internal state tracking. 357 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 358 * <register width> * 8 359 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 360 * shadowed and real data registers writes together. 361 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 362 * safely. 363 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 364 * direction safely. A "1" in this word means the line is set as 365 * output. 366 * 367 * A gpio_chip can help platforms abstract various sources of GPIOs so 368 * they can all be accessed through a common programming interface. 369 * Example sources would be SOC controllers, FPGAs, multifunction 370 * chips, dedicated GPIO expanders, and so on. 371 * 372 * Each chip controls a number of signals, identified in method calls 373 * by "offset" values in the range 0..(@ngpio - 1). When those signals 374 * are referenced through calls like gpio_get_value(gpio), the offset 375 * is calculated by subtracting @base from the gpio number. 376 */ 377 struct gpio_chip { 378 const char *label; 379 struct gpio_device *gpiodev; 380 struct device *parent; 381 struct fwnode_handle *fwnode; 382 struct module *owner; 383 384 int (*request)(struct gpio_chip *gc, 385 unsigned int offset); 386 void (*free)(struct gpio_chip *gc, 387 unsigned int offset); 388 int (*get_direction)(struct gpio_chip *gc, 389 unsigned int offset); 390 int (*direction_input)(struct gpio_chip *gc, 391 unsigned int offset); 392 int (*direction_output)(struct gpio_chip *gc, 393 unsigned int offset, int value); 394 int (*get)(struct gpio_chip *gc, 395 unsigned int offset); 396 int (*get_multiple)(struct gpio_chip *gc, 397 unsigned long *mask, 398 unsigned long *bits); 399 void (*set)(struct gpio_chip *gc, 400 unsigned int offset, int value); 401 void (*set_multiple)(struct gpio_chip *gc, 402 unsigned long *mask, 403 unsigned long *bits); 404 int (*set_config)(struct gpio_chip *gc, 405 unsigned int offset, 406 unsigned long config); 407 int (*to_irq)(struct gpio_chip *gc, 408 unsigned int offset); 409 410 void (*dbg_show)(struct seq_file *s, 411 struct gpio_chip *gc); 412 413 int (*init_valid_mask)(struct gpio_chip *gc, 414 unsigned long *valid_mask, 415 unsigned int ngpios); 416 417 int (*add_pin_ranges)(struct gpio_chip *gc); 418 419 int base; 420 u16 ngpio; 421 u16 offset; 422 const char *const *names; 423 bool can_sleep; 424 425 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 426 unsigned long (*read_reg)(void __iomem *reg); 427 void (*write_reg)(void __iomem *reg, unsigned long data); 428 bool be_bits; 429 void __iomem *reg_dat; 430 void __iomem *reg_set; 431 void __iomem *reg_clr; 432 void __iomem *reg_dir_out; 433 void __iomem *reg_dir_in; 434 bool bgpio_dir_unreadable; 435 int bgpio_bits; 436 spinlock_t bgpio_lock; 437 unsigned long bgpio_data; 438 unsigned long bgpio_dir; 439 #endif /* CONFIG_GPIO_GENERIC */ 440 441 #ifdef CONFIG_GPIOLIB_IRQCHIP 442 /* 443 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 444 * to handle IRQs for most practical cases. 445 */ 446 447 /** 448 * @irq: 449 * 450 * Integrates interrupt chip functionality with the GPIO chip. Can be 451 * used to handle IRQs for most practical cases. 452 */ 453 struct gpio_irq_chip irq; 454 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 455 456 /** 457 * @valid_mask: 458 * 459 * If not %NULL, holds bitmask of GPIOs which are valid to be used 460 * from the chip. 461 */ 462 unsigned long *valid_mask; 463 464 #if defined(CONFIG_OF_GPIO) 465 /* 466 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in 467 * the device tree automatically may have an OF translation 468 */ 469 470 /** 471 * @of_node: 472 * 473 * Pointer to a device tree node representing this GPIO controller. 474 */ 475 struct device_node *of_node; 476 477 /** 478 * @of_gpio_n_cells: 479 * 480 * Number of cells used to form the GPIO specifier. 481 */ 482 unsigned int of_gpio_n_cells; 483 484 /** 485 * @of_xlate: 486 * 487 * Callback to translate a device tree GPIO specifier into a chip- 488 * relative GPIO number and flags. 489 */ 490 int (*of_xlate)(struct gpio_chip *gc, 491 const struct of_phandle_args *gpiospec, u32 *flags); 492 #endif /* CONFIG_OF_GPIO */ 493 }; 494 495 extern const char *gpiochip_is_requested(struct gpio_chip *gc, 496 unsigned int offset); 497 498 /** 499 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range 500 * @chip: the chip to query 501 * @i: loop variable 502 * @base: first GPIO in the range 503 * @size: amount of GPIOs to check starting from @base 504 * @label: label of current GPIO 505 */ 506 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \ 507 for (i = 0; i < size; i++) \ 508 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else 509 510 /* Iterates over all requested GPIO of the given @chip */ 511 #define for_each_requested_gpio(chip, i, label) \ 512 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label) 513 514 /* add/remove chips */ 515 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, 516 struct lock_class_key *lock_key, 517 struct lock_class_key *request_key); 518 519 /** 520 * gpiochip_add_data() - register a gpio_chip 521 * @gc: the chip to register, with gc->base initialized 522 * @data: driver-private data associated with this chip 523 * 524 * Context: potentially before irqs will work 525 * 526 * When gpiochip_add_data() is called very early during boot, so that GPIOs 527 * can be freely used, the gc->parent device must be registered before 528 * the gpio framework's arch_initcall(). Otherwise sysfs initialization 529 * for GPIOs will fail rudely. 530 * 531 * gpiochip_add_data() must only be called after gpiolib initialization, 532 * i.e. after core_initcall(). 533 * 534 * If gc->base is negative, this requests dynamic assignment of 535 * a range of valid GPIOs. 536 * 537 * Returns: 538 * A negative errno if the chip can't be registered, such as because the 539 * gc->base is invalid or already associated with a different chip. 540 * Otherwise it returns zero as a success code. 541 */ 542 #ifdef CONFIG_LOCKDEP 543 #define gpiochip_add_data(gc, data) ({ \ 544 static struct lock_class_key lock_key; \ 545 static struct lock_class_key request_key; \ 546 gpiochip_add_data_with_key(gc, data, &lock_key, \ 547 &request_key); \ 548 }) 549 #define devm_gpiochip_add_data(dev, gc, data) ({ \ 550 static struct lock_class_key lock_key; \ 551 static struct lock_class_key request_key; \ 552 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \ 553 &request_key); \ 554 }) 555 #else 556 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL) 557 #define devm_gpiochip_add_data(dev, gc, data) \ 558 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL) 559 #endif /* CONFIG_LOCKDEP */ 560 561 static inline int gpiochip_add(struct gpio_chip *gc) 562 { 563 return gpiochip_add_data(gc, NULL); 564 } 565 extern void gpiochip_remove(struct gpio_chip *gc); 566 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data, 567 struct lock_class_key *lock_key, 568 struct lock_class_key *request_key); 569 570 extern struct gpio_chip *gpiochip_find(void *data, 571 int (*match)(struct gpio_chip *gc, void *data)); 572 573 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset); 574 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset); 575 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset); 576 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset); 577 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); 578 579 /* Line status inquiry for drivers */ 580 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); 581 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); 582 583 /* Sleep persistence inquiry for drivers */ 584 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset); 585 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset); 586 587 /* get driver data */ 588 void *gpiochip_get_data(struct gpio_chip *gc); 589 590 struct bgpio_pdata { 591 const char *label; 592 int base; 593 int ngpio; 594 }; 595 596 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 597 598 void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, 599 unsigned int parent_hwirq, 600 unsigned int parent_type); 601 void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, 602 unsigned int parent_hwirq, 603 unsigned int parent_type); 604 605 #else 606 607 static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, 608 unsigned int parent_hwirq, 609 unsigned int parent_type) 610 { 611 return NULL; 612 } 613 614 static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, 615 unsigned int parent_hwirq, 616 unsigned int parent_type) 617 { 618 return NULL; 619 } 620 621 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ 622 623 int bgpio_init(struct gpio_chip *gc, struct device *dev, 624 unsigned long sz, void __iomem *dat, void __iomem *set, 625 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 626 unsigned long flags); 627 628 #define BGPIOF_BIG_ENDIAN BIT(0) 629 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 630 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 631 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 632 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 633 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 634 #define BGPIOF_NO_SET_ON_INPUT BIT(6) 635 636 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, 637 irq_hw_number_t hwirq); 638 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq); 639 640 int gpiochip_irq_domain_activate(struct irq_domain *domain, 641 struct irq_data *data, bool reserve); 642 void gpiochip_irq_domain_deactivate(struct irq_domain *domain, 643 struct irq_data *data); 644 645 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc, 646 unsigned int offset); 647 648 #ifdef CONFIG_GPIOLIB_IRQCHIP 649 int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 650 struct irq_domain *domain); 651 #else 652 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 653 struct irq_domain *domain) 654 { 655 WARN_ON(1); 656 return -EINVAL; 657 } 658 #endif 659 660 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset); 661 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset); 662 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset, 663 unsigned long config); 664 665 /** 666 * struct gpio_pin_range - pin range controlled by a gpio chip 667 * @node: list for maintaining set of pin ranges, used internally 668 * @pctldev: pinctrl device which handles corresponding pins 669 * @range: actual range of pins controlled by a gpio controller 670 */ 671 struct gpio_pin_range { 672 struct list_head node; 673 struct pinctrl_dev *pctldev; 674 struct pinctrl_gpio_range range; 675 }; 676 677 #ifdef CONFIG_PINCTRL 678 679 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 680 unsigned int gpio_offset, unsigned int pin_offset, 681 unsigned int npins); 682 int gpiochip_add_pingroup_range(struct gpio_chip *gc, 683 struct pinctrl_dev *pctldev, 684 unsigned int gpio_offset, const char *pin_group); 685 void gpiochip_remove_pin_ranges(struct gpio_chip *gc); 686 687 #else /* ! CONFIG_PINCTRL */ 688 689 static inline int 690 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 691 unsigned int gpio_offset, unsigned int pin_offset, 692 unsigned int npins) 693 { 694 return 0; 695 } 696 static inline int 697 gpiochip_add_pingroup_range(struct gpio_chip *gc, 698 struct pinctrl_dev *pctldev, 699 unsigned int gpio_offset, const char *pin_group) 700 { 701 return 0; 702 } 703 704 static inline void 705 gpiochip_remove_pin_ranges(struct gpio_chip *gc) 706 { 707 } 708 709 #endif /* CONFIG_PINCTRL */ 710 711 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc, 712 unsigned int hwnum, 713 const char *label, 714 enum gpio_lookup_flags lflags, 715 enum gpiod_flags dflags); 716 void gpiochip_free_own_desc(struct gpio_desc *desc); 717 718 #ifdef CONFIG_GPIOLIB 719 720 /* lock/unlock as IRQ */ 721 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset); 722 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset); 723 724 725 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 726 727 #else /* CONFIG_GPIOLIB */ 728 729 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 730 { 731 /* GPIO can never have been requested */ 732 WARN_ON(1); 733 return ERR_PTR(-ENODEV); 734 } 735 736 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc, 737 unsigned int offset) 738 { 739 WARN_ON(1); 740 return -EINVAL; 741 } 742 743 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc, 744 unsigned int offset) 745 { 746 WARN_ON(1); 747 } 748 #endif /* CONFIG_GPIOLIB */ 749 750 #endif /* __LINUX_GPIO_DRIVER_H */ 751