1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_GPIO_DRIVER_H 3 #define __LINUX_GPIO_DRIVER_H 4 5 #include <linux/bits.h> 6 #include <linux/irqchip/chained_irq.h> 7 #include <linux/irqdomain.h> 8 #include <linux/irqhandler.h> 9 #include <linux/lockdep.h> 10 #include <linux/pinctrl/pinconf-generic.h> 11 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/property.h> 13 #include <linux/spinlock_types.h> 14 #include <linux/types.h> 15 16 #ifdef CONFIG_GENERIC_MSI_IRQ 17 #include <asm/msi.h> 18 #endif 19 20 struct device; 21 struct irq_chip; 22 struct irq_data; 23 struct module; 24 struct of_phandle_args; 25 struct pinctrl_dev; 26 struct seq_file; 27 28 struct gpio_chip; 29 struct gpio_desc; 30 struct gpio_device; 31 32 enum gpio_lookup_flags; 33 enum gpiod_flags; 34 35 union gpio_irq_fwspec { 36 struct irq_fwspec fwspec; 37 #ifdef CONFIG_GENERIC_MSI_IRQ 38 msi_alloc_info_t msiinfo; 39 #endif 40 }; 41 42 #define GPIO_LINE_DIRECTION_IN 1 43 #define GPIO_LINE_DIRECTION_OUT 0 44 45 /** 46 * struct gpio_irq_chip - GPIO interrupt controller 47 */ 48 struct gpio_irq_chip { 49 /** 50 * @chip: 51 * 52 * GPIO IRQ chip implementation, provided by GPIO driver. 53 */ 54 struct irq_chip *chip; 55 56 /** 57 * @domain: 58 * 59 * Interrupt translation domain; responsible for mapping between GPIO 60 * hwirq number and Linux IRQ number. 61 */ 62 struct irq_domain *domain; 63 64 /** 65 * @domain_ops: 66 * 67 * Table of interrupt domain operations for this IRQ chip. 68 */ 69 const struct irq_domain_ops *domain_ops; 70 71 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 72 /** 73 * @fwnode: 74 * 75 * Firmware node corresponding to this gpiochip/irqchip, necessary 76 * for hierarchical irqdomain support. 77 */ 78 struct fwnode_handle *fwnode; 79 80 /** 81 * @parent_domain: 82 * 83 * If non-NULL, will be set as the parent of this GPIO interrupt 84 * controller's IRQ domain to establish a hierarchical interrupt 85 * domain. The presence of this will activate the hierarchical 86 * interrupt support. 87 */ 88 struct irq_domain *parent_domain; 89 90 /** 91 * @child_to_parent_hwirq: 92 * 93 * This callback translates a child hardware IRQ offset to a parent 94 * hardware IRQ offset on a hierarchical interrupt chip. The child 95 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the 96 * ngpio field of struct gpio_chip) and the corresponding parent 97 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by 98 * the driver. The driver can calculate this from an offset or using 99 * a lookup table or whatever method is best for this chip. Return 100 * 0 on successful translation in the driver. 101 * 102 * If some ranges of hardware IRQs do not have a corresponding parent 103 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and 104 * @need_valid_mask to make these GPIO lines unavailable for 105 * translation. 106 */ 107 int (*child_to_parent_hwirq)(struct gpio_chip *gc, 108 unsigned int child_hwirq, 109 unsigned int child_type, 110 unsigned int *parent_hwirq, 111 unsigned int *parent_type); 112 113 /** 114 * @populate_parent_alloc_arg : 115 * 116 * This optional callback allocates and populates the specific struct 117 * for the parent's IRQ domain. If this is not specified, then 118 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell 119 * variant named &gpiochip_populate_parent_fwspec_fourcell is also 120 * available. 121 */ 122 int (*populate_parent_alloc_arg)(struct gpio_chip *gc, 123 union gpio_irq_fwspec *fwspec, 124 unsigned int parent_hwirq, 125 unsigned int parent_type); 126 127 /** 128 * @child_offset_to_irq: 129 * 130 * This optional callback is used to translate the child's GPIO line 131 * offset on the GPIO chip to an IRQ number for the GPIO to_irq() 132 * callback. If this is not specified, then a default callback will be 133 * provided that returns the line offset. 134 */ 135 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc, 136 unsigned int pin); 137 138 /** 139 * @child_irq_domain_ops: 140 * 141 * The IRQ domain operations that will be used for this GPIO IRQ 142 * chip. If no operations are provided, then default callbacks will 143 * be populated to setup the IRQ hierarchy. Some drivers need to 144 * supply their own translate function. 145 */ 146 struct irq_domain_ops child_irq_domain_ops; 147 #endif 148 149 /** 150 * @handler: 151 * 152 * The IRQ handler to use (often a predefined IRQ core function) for 153 * GPIO IRQs, provided by GPIO driver. 154 */ 155 irq_flow_handler_t handler; 156 157 /** 158 * @default_type: 159 * 160 * Default IRQ triggering type applied during GPIO driver 161 * initialization, provided by GPIO driver. 162 */ 163 unsigned int default_type; 164 165 /** 166 * @lock_key: 167 * 168 * Per GPIO IRQ chip lockdep class for IRQ lock. 169 */ 170 struct lock_class_key *lock_key; 171 172 /** 173 * @request_key: 174 * 175 * Per GPIO IRQ chip lockdep class for IRQ request. 176 */ 177 struct lock_class_key *request_key; 178 179 /** 180 * @parent_handler: 181 * 182 * The interrupt handler for the GPIO chip's parent interrupts, may be 183 * NULL if the parent interrupts are nested rather than cascaded. 184 */ 185 irq_flow_handler_t parent_handler; 186 187 union { 188 /** 189 * @parent_handler_data: 190 * 191 * If @per_parent_data is false, @parent_handler_data is a 192 * single pointer used as the data associated with every 193 * parent interrupt. 194 */ 195 void *parent_handler_data; 196 197 /** 198 * @parent_handler_data_array: 199 * 200 * If @per_parent_data is true, @parent_handler_data_array is 201 * an array of @num_parents pointers, and is used to associate 202 * different data for each parent. This cannot be NULL if 203 * @per_parent_data is true. 204 */ 205 void **parent_handler_data_array; 206 }; 207 208 /** 209 * @num_parents: 210 * 211 * The number of interrupt parents of a GPIO chip. 212 */ 213 unsigned int num_parents; 214 215 /** 216 * @parents: 217 * 218 * A list of interrupt parents of a GPIO chip. This is owned by the 219 * driver, so the core will only reference this list, not modify it. 220 */ 221 unsigned int *parents; 222 223 /** 224 * @map: 225 * 226 * A list of interrupt parents for each line of a GPIO chip. 227 */ 228 unsigned int *map; 229 230 /** 231 * @threaded: 232 * 233 * True if set the interrupt handling uses nested threads. 234 */ 235 bool threaded; 236 237 /** 238 * @per_parent_data: 239 * 240 * True if parent_handler_data_array describes a @num_parents 241 * sized array to be used as parent data. 242 */ 243 bool per_parent_data; 244 245 /** 246 * @initialized: 247 * 248 * Flag to track GPIO chip irq member's initialization. 249 * This flag will make sure GPIO chip irq members are not used 250 * before they are initialized. 251 */ 252 bool initialized; 253 254 /** 255 * @domain_is_allocated_externally: 256 * 257 * True it the irq_domain was allocated outside of gpiolib, in which 258 * case gpiolib won't free the irq_domain itself. 259 */ 260 bool domain_is_allocated_externally; 261 262 /** 263 * @init_hw: optional routine to initialize hardware before 264 * an IRQ chip will be added. This is quite useful when 265 * a particular driver wants to clear IRQ related registers 266 * in order to avoid undesired events. 267 */ 268 int (*init_hw)(struct gpio_chip *gc); 269 270 /** 271 * @init_valid_mask: optional routine to initialize @valid_mask, to be 272 * used if not all GPIO lines are valid interrupts. Sometimes some 273 * lines just cannot fire interrupts, and this routine, when defined, 274 * is passed a bitmap in "valid_mask" and it will have ngpios 275 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can 276 * then directly set some bits to "0" if they cannot be used for 277 * interrupts. 278 */ 279 void (*init_valid_mask)(struct gpio_chip *gc, 280 unsigned long *valid_mask, 281 unsigned int ngpios); 282 283 /** 284 * @valid_mask: 285 * 286 * If not %NULL, holds bitmask of GPIOs which are valid to be included 287 * in IRQ domain of the chip. 288 */ 289 unsigned long *valid_mask; 290 291 /** 292 * @first: 293 * 294 * Required for static IRQ allocation. If set, irq_domain_add_simple() 295 * will allocate and map all IRQs during initialization. 296 */ 297 unsigned int first; 298 299 /** 300 * @irq_enable: 301 * 302 * Store old irq_chip irq_enable callback 303 */ 304 void (*irq_enable)(struct irq_data *data); 305 306 /** 307 * @irq_disable: 308 * 309 * Store old irq_chip irq_disable callback 310 */ 311 void (*irq_disable)(struct irq_data *data); 312 /** 313 * @irq_unmask: 314 * 315 * Store old irq_chip irq_unmask callback 316 */ 317 void (*irq_unmask)(struct irq_data *data); 318 319 /** 320 * @irq_mask: 321 * 322 * Store old irq_chip irq_mask callback 323 */ 324 void (*irq_mask)(struct irq_data *data); 325 }; 326 327 /** 328 * struct gpio_chip - abstract a GPIO controller 329 * @label: a functional name for the GPIO device, such as a part 330 * number or the name of the SoC IP-block implementing it. 331 * @gpiodev: the internal state holder, opaque struct 332 * @parent: optional parent device providing the GPIOs 333 * @fwnode: optional fwnode providing this controller's properties 334 * @owner: helps prevent removal of modules exporting active GPIOs 335 * @request: optional hook for chip-specific activation, such as 336 * enabling module power and clock; may sleep 337 * @free: optional hook for chip-specific deactivation, such as 338 * disabling module power and clock; may sleep 339 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 340 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN), 341 * or negative error. It is recommended to always implement this 342 * function, even on input-only or output-only gpio chips. 343 * @direction_input: configures signal "offset" as input, or returns error 344 * This can be omitted on input-only or output-only gpio chips. 345 * @direction_output: configures signal "offset" as output, or returns error 346 * This can be omitted on input-only or output-only gpio chips. 347 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 348 * @get_multiple: reads values for multiple signals defined by "mask" and 349 * stores them in "bits", returns 0 on success or negative error 350 * @set: assigns output value for signal "offset" 351 * @set_multiple: assigns output values for multiple signals defined by "mask" 352 * @set_config: optional hook for all kinds of settings. Uses the same 353 * packed config format as generic pinconf. 354 * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings; 355 * implementation may not sleep 356 * @dbg_show: optional routine to show contents in debugfs; default code 357 * will be used when this is omitted, but custom code can show extra 358 * state (such as pullup/pulldown configuration). 359 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if 360 * not all GPIOs are valid. 361 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when 362 * requires special mapping of the pins that provides GPIO functionality. 363 * It is called after adding GPIO chip and before adding IRQ chip. 364 * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to 365 * enable hardware timestamp. 366 * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to 367 * disable hardware timestamp. 368 * @base: identifies the first GPIO number handled by this chip; 369 * or, if negative during registration, requests dynamic ID allocation. 370 * DEPRECATION: providing anything non-negative and nailing the base 371 * offset of GPIO chips is deprecated. Please pass -1 as base to 372 * let gpiolib select the chip base in all possible cases. We want to 373 * get rid of the static GPIO number space in the long run. 374 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 375 * handled is (base + ngpio - 1). 376 * @offset: when multiple gpio chips belong to the same device this 377 * can be used as offset within the device so friendly names can 378 * be properly assigned. 379 * @names: if set, must be an array of strings to use as alternative 380 * names for the GPIOs in this chip. Any entry in the array 381 * may be NULL if there is no alias for the GPIO, however the 382 * array must be @ngpio entries long. A name can include a single printk 383 * format specifier for an unsigned int. It is substituted by the actual 384 * number of the gpio. 385 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 386 * must while accessing GPIO expander chips over I2C or SPI. This 387 * implies that if the chip supports IRQs, these IRQs need to be threaded 388 * as the chip access may sleep when e.g. reading out the IRQ status 389 * registers. 390 * @read_reg: reader function for generic GPIO 391 * @write_reg: writer function for generic GPIO 392 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing 393 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the 394 * generic GPIO core. It is for internal housekeeping only. 395 * @reg_dat: data (in) register for generic GPIO 396 * @reg_set: output set register (out=high) for generic GPIO 397 * @reg_clr: output clear register (out=low) for generic GPIO 398 * @reg_dir_out: direction out setting register for generic GPIO 399 * @reg_dir_in: direction in setting register for generic GPIO 400 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 401 * be read and we need to rely on out internal state tracking. 402 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 403 * <register width> * 8 404 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 405 * shadowed and real data registers writes together. 406 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 407 * safely. 408 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 409 * direction safely. A "1" in this word means the line is set as 410 * output. 411 * 412 * A gpio_chip can help platforms abstract various sources of GPIOs so 413 * they can all be accessed through a common programming interface. 414 * Example sources would be SOC controllers, FPGAs, multifunction 415 * chips, dedicated GPIO expanders, and so on. 416 * 417 * Each chip controls a number of signals, identified in method calls 418 * by "offset" values in the range 0..(@ngpio - 1). When those signals 419 * are referenced through calls like gpio_get_value(gpio), the offset 420 * is calculated by subtracting @base from the gpio number. 421 */ 422 struct gpio_chip { 423 const char *label; 424 struct gpio_device *gpiodev; 425 struct device *parent; 426 struct fwnode_handle *fwnode; 427 struct module *owner; 428 429 int (*request)(struct gpio_chip *gc, 430 unsigned int offset); 431 void (*free)(struct gpio_chip *gc, 432 unsigned int offset); 433 int (*get_direction)(struct gpio_chip *gc, 434 unsigned int offset); 435 int (*direction_input)(struct gpio_chip *gc, 436 unsigned int offset); 437 int (*direction_output)(struct gpio_chip *gc, 438 unsigned int offset, int value); 439 int (*get)(struct gpio_chip *gc, 440 unsigned int offset); 441 int (*get_multiple)(struct gpio_chip *gc, 442 unsigned long *mask, 443 unsigned long *bits); 444 void (*set)(struct gpio_chip *gc, 445 unsigned int offset, int value); 446 void (*set_multiple)(struct gpio_chip *gc, 447 unsigned long *mask, 448 unsigned long *bits); 449 int (*set_config)(struct gpio_chip *gc, 450 unsigned int offset, 451 unsigned long config); 452 int (*to_irq)(struct gpio_chip *gc, 453 unsigned int offset); 454 455 void (*dbg_show)(struct seq_file *s, 456 struct gpio_chip *gc); 457 458 int (*init_valid_mask)(struct gpio_chip *gc, 459 unsigned long *valid_mask, 460 unsigned int ngpios); 461 462 int (*add_pin_ranges)(struct gpio_chip *gc); 463 464 int (*en_hw_timestamp)(struct gpio_chip *gc, 465 u32 offset, 466 unsigned long flags); 467 int (*dis_hw_timestamp)(struct gpio_chip *gc, 468 u32 offset, 469 unsigned long flags); 470 int base; 471 u16 ngpio; 472 u16 offset; 473 const char *const *names; 474 bool can_sleep; 475 476 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 477 unsigned long (*read_reg)(void __iomem *reg); 478 void (*write_reg)(void __iomem *reg, unsigned long data); 479 bool be_bits; 480 void __iomem *reg_dat; 481 void __iomem *reg_set; 482 void __iomem *reg_clr; 483 void __iomem *reg_dir_out; 484 void __iomem *reg_dir_in; 485 bool bgpio_dir_unreadable; 486 int bgpio_bits; 487 raw_spinlock_t bgpio_lock; 488 unsigned long bgpio_data; 489 unsigned long bgpio_dir; 490 #endif /* CONFIG_GPIO_GENERIC */ 491 492 #ifdef CONFIG_GPIOLIB_IRQCHIP 493 /* 494 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 495 * to handle IRQs for most practical cases. 496 */ 497 498 /** 499 * @irq: 500 * 501 * Integrates interrupt chip functionality with the GPIO chip. Can be 502 * used to handle IRQs for most practical cases. 503 */ 504 struct gpio_irq_chip irq; 505 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 506 507 /** 508 * @valid_mask: 509 * 510 * If not %NULL, holds bitmask of GPIOs which are valid to be used 511 * from the chip. 512 */ 513 unsigned long *valid_mask; 514 515 #if defined(CONFIG_OF_GPIO) 516 /* 517 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in 518 * the device tree automatically may have an OF translation 519 */ 520 521 /** 522 * @of_gpio_n_cells: 523 * 524 * Number of cells used to form the GPIO specifier. 525 */ 526 unsigned int of_gpio_n_cells; 527 528 /** 529 * @of_xlate: 530 * 531 * Callback to translate a device tree GPIO specifier into a chip- 532 * relative GPIO number and flags. 533 */ 534 int (*of_xlate)(struct gpio_chip *gc, 535 const struct of_phandle_args *gpiospec, u32 *flags); 536 #endif /* CONFIG_OF_GPIO */ 537 }; 538 539 extern const char *gpiochip_is_requested(struct gpio_chip *gc, 540 unsigned int offset); 541 542 /** 543 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range 544 * @chip: the chip to query 545 * @i: loop variable 546 * @base: first GPIO in the range 547 * @size: amount of GPIOs to check starting from @base 548 * @label: label of current GPIO 549 */ 550 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \ 551 for (i = 0; i < size; i++) \ 552 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else 553 554 /* Iterates over all requested GPIO of the given @chip */ 555 #define for_each_requested_gpio(chip, i, label) \ 556 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label) 557 558 /* add/remove chips */ 559 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, 560 struct lock_class_key *lock_key, 561 struct lock_class_key *request_key); 562 563 /** 564 * gpiochip_add_data() - register a gpio_chip 565 * @gc: the chip to register, with gc->base initialized 566 * @data: driver-private data associated with this chip 567 * 568 * Context: potentially before irqs will work 569 * 570 * When gpiochip_add_data() is called very early during boot, so that GPIOs 571 * can be freely used, the gc->parent device must be registered before 572 * the gpio framework's arch_initcall(). Otherwise sysfs initialization 573 * for GPIOs will fail rudely. 574 * 575 * gpiochip_add_data() must only be called after gpiolib initialization, 576 * i.e. after core_initcall(). 577 * 578 * If gc->base is negative, this requests dynamic assignment of 579 * a range of valid GPIOs. 580 * 581 * Returns: 582 * A negative errno if the chip can't be registered, such as because the 583 * gc->base is invalid or already associated with a different chip. 584 * Otherwise it returns zero as a success code. 585 */ 586 #ifdef CONFIG_LOCKDEP 587 #define gpiochip_add_data(gc, data) ({ \ 588 static struct lock_class_key lock_key; \ 589 static struct lock_class_key request_key; \ 590 gpiochip_add_data_with_key(gc, data, &lock_key, \ 591 &request_key); \ 592 }) 593 #define devm_gpiochip_add_data(dev, gc, data) ({ \ 594 static struct lock_class_key lock_key; \ 595 static struct lock_class_key request_key; \ 596 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \ 597 &request_key); \ 598 }) 599 #else 600 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL) 601 #define devm_gpiochip_add_data(dev, gc, data) \ 602 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL) 603 #endif /* CONFIG_LOCKDEP */ 604 605 static inline int gpiochip_add(struct gpio_chip *gc) 606 { 607 return gpiochip_add_data(gc, NULL); 608 } 609 extern void gpiochip_remove(struct gpio_chip *gc); 610 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data, 611 struct lock_class_key *lock_key, 612 struct lock_class_key *request_key); 613 614 extern struct gpio_chip *gpiochip_find(void *data, 615 int (*match)(struct gpio_chip *gc, void *data)); 616 617 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset); 618 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset); 619 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset); 620 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset); 621 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); 622 623 /* irq_data versions of the above */ 624 int gpiochip_irq_reqres(struct irq_data *data); 625 void gpiochip_irq_relres(struct irq_data *data); 626 627 /* Paste this in your irq_chip structure */ 628 #define GPIOCHIP_IRQ_RESOURCE_HELPERS \ 629 .irq_request_resources = gpiochip_irq_reqres, \ 630 .irq_release_resources = gpiochip_irq_relres 631 632 static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq, 633 const struct irq_chip *chip) 634 { 635 /* Yes, dropping const is ugly, but it isn't like we have a choice */ 636 girq->chip = (struct irq_chip *)chip; 637 } 638 639 /* Line status inquiry for drivers */ 640 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); 641 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); 642 643 /* Sleep persistence inquiry for drivers */ 644 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset); 645 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset); 646 647 /* get driver data */ 648 void *gpiochip_get_data(struct gpio_chip *gc); 649 650 struct bgpio_pdata { 651 const char *label; 652 int base; 653 int ngpio; 654 }; 655 656 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 657 658 int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, 659 union gpio_irq_fwspec *gfwspec, 660 unsigned int parent_hwirq, 661 unsigned int parent_type); 662 int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, 663 union gpio_irq_fwspec *gfwspec, 664 unsigned int parent_hwirq, 665 unsigned int parent_type); 666 667 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ 668 669 int bgpio_init(struct gpio_chip *gc, struct device *dev, 670 unsigned long sz, void __iomem *dat, void __iomem *set, 671 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 672 unsigned long flags); 673 674 #define BGPIOF_BIG_ENDIAN BIT(0) 675 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 676 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 677 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 678 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 679 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 680 #define BGPIOF_NO_SET_ON_INPUT BIT(6) 681 682 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, 683 irq_hw_number_t hwirq); 684 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq); 685 686 int gpiochip_irq_domain_activate(struct irq_domain *domain, 687 struct irq_data *data, bool reserve); 688 void gpiochip_irq_domain_deactivate(struct irq_domain *domain, 689 struct irq_data *data); 690 691 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc, 692 unsigned int offset); 693 694 #ifdef CONFIG_GPIOLIB_IRQCHIP 695 int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 696 struct irq_domain *domain); 697 #else 698 699 #include <asm/bug.h> 700 #include <asm/errno.h> 701 702 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 703 struct irq_domain *domain) 704 { 705 WARN_ON(1); 706 return -EINVAL; 707 } 708 #endif 709 710 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset); 711 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset); 712 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset, 713 unsigned long config); 714 715 /** 716 * struct gpio_pin_range - pin range controlled by a gpio chip 717 * @node: list for maintaining set of pin ranges, used internally 718 * @pctldev: pinctrl device which handles corresponding pins 719 * @range: actual range of pins controlled by a gpio controller 720 */ 721 struct gpio_pin_range { 722 struct list_head node; 723 struct pinctrl_dev *pctldev; 724 struct pinctrl_gpio_range range; 725 }; 726 727 #ifdef CONFIG_PINCTRL 728 729 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 730 unsigned int gpio_offset, unsigned int pin_offset, 731 unsigned int npins); 732 int gpiochip_add_pingroup_range(struct gpio_chip *gc, 733 struct pinctrl_dev *pctldev, 734 unsigned int gpio_offset, const char *pin_group); 735 void gpiochip_remove_pin_ranges(struct gpio_chip *gc); 736 737 #else /* ! CONFIG_PINCTRL */ 738 739 static inline int 740 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 741 unsigned int gpio_offset, unsigned int pin_offset, 742 unsigned int npins) 743 { 744 return 0; 745 } 746 static inline int 747 gpiochip_add_pingroup_range(struct gpio_chip *gc, 748 struct pinctrl_dev *pctldev, 749 unsigned int gpio_offset, const char *pin_group) 750 { 751 return 0; 752 } 753 754 static inline void 755 gpiochip_remove_pin_ranges(struct gpio_chip *gc) 756 { 757 } 758 759 #endif /* CONFIG_PINCTRL */ 760 761 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc, 762 unsigned int hwnum, 763 const char *label, 764 enum gpio_lookup_flags lflags, 765 enum gpiod_flags dflags); 766 void gpiochip_free_own_desc(struct gpio_desc *desc); 767 768 #ifdef CONFIG_GPIOLIB 769 770 /* lock/unlock as IRQ */ 771 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset); 772 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset); 773 774 775 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 776 777 #else /* CONFIG_GPIOLIB */ 778 779 #include <linux/err.h> 780 781 #include <asm/bug.h> 782 783 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 784 { 785 /* GPIO can never have been requested */ 786 WARN_ON(1); 787 return ERR_PTR(-ENODEV); 788 } 789 790 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc, 791 unsigned int offset) 792 { 793 WARN_ON(1); 794 return -EINVAL; 795 } 796 797 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc, 798 unsigned int offset) 799 { 800 WARN_ON(1); 801 } 802 #endif /* CONFIG_GPIOLIB */ 803 804 #define for_each_gpiochip_node(dev, child) \ 805 device_for_each_child_node(dev, child) \ 806 if (!fwnode_property_present(child, "gpio-controller")) {} else 807 808 static inline unsigned int gpiochip_node_count(struct device *dev) 809 { 810 struct fwnode_handle *child; 811 unsigned int count = 0; 812 813 for_each_gpiochip_node(dev, child) 814 count++; 815 816 return count; 817 } 818 819 static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev) 820 { 821 struct fwnode_handle *fwnode; 822 823 for_each_gpiochip_node(dev, fwnode) 824 return fwnode; 825 826 return NULL; 827 } 828 829 #endif /* __LINUX_GPIO_DRIVER_H */ 830