1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_GPIO_DRIVER_H 3 #define __LINUX_GPIO_DRIVER_H 4 5 #include <linux/device.h> 6 #include <linux/types.h> 7 #include <linux/irq.h> 8 #include <linux/irqchip/chained_irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/lockdep.h> 11 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 14 struct gpio_desc; 15 struct of_phandle_args; 16 struct device_node; 17 struct seq_file; 18 struct gpio_device; 19 struct module; 20 enum gpiod_flags; 21 enum gpio_lookup_flags; 22 23 struct gpio_chip; 24 25 #define GPIO_LINE_DIRECTION_IN 1 26 #define GPIO_LINE_DIRECTION_OUT 0 27 28 /** 29 * struct gpio_irq_chip - GPIO interrupt controller 30 */ 31 struct gpio_irq_chip { 32 /** 33 * @chip: 34 * 35 * GPIO IRQ chip implementation, provided by GPIO driver. 36 */ 37 struct irq_chip *chip; 38 39 /** 40 * @domain: 41 * 42 * Interrupt translation domain; responsible for mapping between GPIO 43 * hwirq number and Linux IRQ number. 44 */ 45 struct irq_domain *domain; 46 47 /** 48 * @domain_ops: 49 * 50 * Table of interrupt domain operations for this IRQ chip. 51 */ 52 const struct irq_domain_ops *domain_ops; 53 54 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 55 /** 56 * @fwnode: 57 * 58 * Firmware node corresponding to this gpiochip/irqchip, necessary 59 * for hierarchical irqdomain support. 60 */ 61 struct fwnode_handle *fwnode; 62 63 /** 64 * @parent_domain: 65 * 66 * If non-NULL, will be set as the parent of this GPIO interrupt 67 * controller's IRQ domain to establish a hierarchical interrupt 68 * domain. The presence of this will activate the hierarchical 69 * interrupt support. 70 */ 71 struct irq_domain *parent_domain; 72 73 /** 74 * @child_to_parent_hwirq: 75 * 76 * This callback translates a child hardware IRQ offset to a parent 77 * hardware IRQ offset on a hierarchical interrupt chip. The child 78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the 79 * ngpio field of struct gpio_chip) and the corresponding parent 80 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by 81 * the driver. The driver can calculate this from an offset or using 82 * a lookup table or whatever method is best for this chip. Return 83 * 0 on successful translation in the driver. 84 * 85 * If some ranges of hardware IRQs do not have a corresponding parent 86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and 87 * @need_valid_mask to make these GPIO lines unavailable for 88 * translation. 89 */ 90 int (*child_to_parent_hwirq)(struct gpio_chip *gc, 91 unsigned int child_hwirq, 92 unsigned int child_type, 93 unsigned int *parent_hwirq, 94 unsigned int *parent_type); 95 96 /** 97 * @populate_parent_alloc_arg : 98 * 99 * This optional callback allocates and populates the specific struct 100 * for the parent's IRQ domain. If this is not specified, then 101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell 102 * variant named &gpiochip_populate_parent_fwspec_fourcell is also 103 * available. 104 */ 105 void *(*populate_parent_alloc_arg)(struct gpio_chip *gc, 106 unsigned int parent_hwirq, 107 unsigned int parent_type); 108 109 /** 110 * @child_offset_to_irq: 111 * 112 * This optional callback is used to translate the child's GPIO line 113 * offset on the GPIO chip to an IRQ number for the GPIO to_irq() 114 * callback. If this is not specified, then a default callback will be 115 * provided that returns the line offset. 116 */ 117 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc, 118 unsigned int pin); 119 120 /** 121 * @child_irq_domain_ops: 122 * 123 * The IRQ domain operations that will be used for this GPIO IRQ 124 * chip. If no operations are provided, then default callbacks will 125 * be populated to setup the IRQ hierarchy. Some drivers need to 126 * supply their own translate function. 127 */ 128 struct irq_domain_ops child_irq_domain_ops; 129 #endif 130 131 /** 132 * @handler: 133 * 134 * The IRQ handler to use (often a predefined IRQ core function) for 135 * GPIO IRQs, provided by GPIO driver. 136 */ 137 irq_flow_handler_t handler; 138 139 /** 140 * @default_type: 141 * 142 * Default IRQ triggering type applied during GPIO driver 143 * initialization, provided by GPIO driver. 144 */ 145 unsigned int default_type; 146 147 /** 148 * @lock_key: 149 * 150 * Per GPIO IRQ chip lockdep class for IRQ lock. 151 */ 152 struct lock_class_key *lock_key; 153 154 /** 155 * @request_key: 156 * 157 * Per GPIO IRQ chip lockdep class for IRQ request. 158 */ 159 struct lock_class_key *request_key; 160 161 /** 162 * @parent_handler: 163 * 164 * The interrupt handler for the GPIO chip's parent interrupts, may be 165 * NULL if the parent interrupts are nested rather than cascaded. 166 */ 167 irq_flow_handler_t parent_handler; 168 169 /** 170 * @parent_handler_data: 171 * 172 * Data associated, and passed to, the handler for the parent 173 * interrupt. 174 */ 175 void *parent_handler_data; 176 177 /** 178 * @num_parents: 179 * 180 * The number of interrupt parents of a GPIO chip. 181 */ 182 unsigned int num_parents; 183 184 /** 185 * @parents: 186 * 187 * A list of interrupt parents of a GPIO chip. This is owned by the 188 * driver, so the core will only reference this list, not modify it. 189 */ 190 unsigned int *parents; 191 192 /** 193 * @map: 194 * 195 * A list of interrupt parents for each line of a GPIO chip. 196 */ 197 unsigned int *map; 198 199 /** 200 * @threaded: 201 * 202 * True if set the interrupt handling uses nested threads. 203 */ 204 bool threaded; 205 206 /** 207 * @init_hw: optional routine to initialize hardware before 208 * an IRQ chip will be added. This is quite useful when 209 * a particular driver wants to clear IRQ related registers 210 * in order to avoid undesired events. 211 */ 212 int (*init_hw)(struct gpio_chip *gc); 213 214 /** 215 * @init_valid_mask: optional routine to initialize @valid_mask, to be 216 * used if not all GPIO lines are valid interrupts. Sometimes some 217 * lines just cannot fire interrupts, and this routine, when defined, 218 * is passed a bitmap in "valid_mask" and it will have ngpios 219 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can 220 * then directly set some bits to "0" if they cannot be used for 221 * interrupts. 222 */ 223 void (*init_valid_mask)(struct gpio_chip *gc, 224 unsigned long *valid_mask, 225 unsigned int ngpios); 226 227 /** 228 * @valid_mask: 229 * 230 * If not %NULL, holds bitmask of GPIOs which are valid to be included 231 * in IRQ domain of the chip. 232 */ 233 unsigned long *valid_mask; 234 235 /** 236 * @first: 237 * 238 * Required for static IRQ allocation. If set, irq_domain_add_simple() 239 * will allocate and map all IRQs during initialization. 240 */ 241 unsigned int first; 242 243 /** 244 * @irq_enable: 245 * 246 * Store old irq_chip irq_enable callback 247 */ 248 void (*irq_enable)(struct irq_data *data); 249 250 /** 251 * @irq_disable: 252 * 253 * Store old irq_chip irq_disable callback 254 */ 255 void (*irq_disable)(struct irq_data *data); 256 /** 257 * @irq_unmask: 258 * 259 * Store old irq_chip irq_unmask callback 260 */ 261 void (*irq_unmask)(struct irq_data *data); 262 263 /** 264 * @irq_mask: 265 * 266 * Store old irq_chip irq_mask callback 267 */ 268 void (*irq_mask)(struct irq_data *data); 269 }; 270 271 /** 272 * struct gpio_chip - abstract a GPIO controller 273 * @label: a functional name for the GPIO device, such as a part 274 * number or the name of the SoC IP-block implementing it. 275 * @gpiodev: the internal state holder, opaque struct 276 * @parent: optional parent device providing the GPIOs 277 * @owner: helps prevent removal of modules exporting active GPIOs 278 * @request: optional hook for chip-specific activation, such as 279 * enabling module power and clock; may sleep 280 * @free: optional hook for chip-specific deactivation, such as 281 * disabling module power and clock; may sleep 282 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 283 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN), 284 * or negative error. It is recommended to always implement this 285 * function, even on input-only or output-only gpio chips. 286 * @direction_input: configures signal "offset" as input, or returns error 287 * This can be omitted on input-only or output-only gpio chips. 288 * @direction_output: configures signal "offset" as output, or returns error 289 * This can be omitted on input-only or output-only gpio chips. 290 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 291 * @get_multiple: reads values for multiple signals defined by "mask" and 292 * stores them in "bits", returns 0 on success or negative error 293 * @set: assigns output value for signal "offset" 294 * @set_multiple: assigns output values for multiple signals defined by "mask" 295 * @set_config: optional hook for all kinds of settings. Uses the same 296 * packed config format as generic pinconf. 297 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings; 298 * implementation may not sleep 299 * @dbg_show: optional routine to show contents in debugfs; default code 300 * will be used when this is omitted, but custom code can show extra 301 * state (such as pullup/pulldown configuration). 302 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if 303 * not all GPIOs are valid. 304 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when 305 * requires special mapping of the pins that provides GPIO functionality. 306 * It is called after adding GPIO chip and before adding IRQ chip. 307 * @base: identifies the first GPIO number handled by this chip; 308 * or, if negative during registration, requests dynamic ID allocation. 309 * DEPRECATION: providing anything non-negative and nailing the base 310 * offset of GPIO chips is deprecated. Please pass -1 as base to 311 * let gpiolib select the chip base in all possible cases. We want to 312 * get rid of the static GPIO number space in the long run. 313 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 314 * handled is (base + ngpio - 1). 315 * @offset: when multiple gpio chips belong to the same device this 316 * can be used as offset within the device so friendly names can 317 * be properly assigned. 318 * @names: if set, must be an array of strings to use as alternative 319 * names for the GPIOs in this chip. Any entry in the array 320 * may be NULL if there is no alias for the GPIO, however the 321 * array must be @ngpio entries long. A name can include a single printk 322 * format specifier for an unsigned int. It is substituted by the actual 323 * number of the gpio. 324 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 325 * must while accessing GPIO expander chips over I2C or SPI. This 326 * implies that if the chip supports IRQs, these IRQs need to be threaded 327 * as the chip access may sleep when e.g. reading out the IRQ status 328 * registers. 329 * @read_reg: reader function for generic GPIO 330 * @write_reg: writer function for generic GPIO 331 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing 332 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the 333 * generic GPIO core. It is for internal housekeeping only. 334 * @reg_dat: data (in) register for generic GPIO 335 * @reg_set: output set register (out=high) for generic GPIO 336 * @reg_clr: output clear register (out=low) for generic GPIO 337 * @reg_dir_out: direction out setting register for generic GPIO 338 * @reg_dir_in: direction in setting register for generic GPIO 339 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 340 * be read and we need to rely on out internal state tracking. 341 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 342 * <register width> * 8 343 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 344 * shadowed and real data registers writes together. 345 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 346 * safely. 347 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 348 * direction safely. A "1" in this word means the line is set as 349 * output. 350 * 351 * A gpio_chip can help platforms abstract various sources of GPIOs so 352 * they can all be accessed through a common programming interface. 353 * Example sources would be SOC controllers, FPGAs, multifunction 354 * chips, dedicated GPIO expanders, and so on. 355 * 356 * Each chip controls a number of signals, identified in method calls 357 * by "offset" values in the range 0..(@ngpio - 1). When those signals 358 * are referenced through calls like gpio_get_value(gpio), the offset 359 * is calculated by subtracting @base from the gpio number. 360 */ 361 struct gpio_chip { 362 const char *label; 363 struct gpio_device *gpiodev; 364 struct device *parent; 365 struct module *owner; 366 367 int (*request)(struct gpio_chip *gc, 368 unsigned int offset); 369 void (*free)(struct gpio_chip *gc, 370 unsigned int offset); 371 int (*get_direction)(struct gpio_chip *gc, 372 unsigned int offset); 373 int (*direction_input)(struct gpio_chip *gc, 374 unsigned int offset); 375 int (*direction_output)(struct gpio_chip *gc, 376 unsigned int offset, int value); 377 int (*get)(struct gpio_chip *gc, 378 unsigned int offset); 379 int (*get_multiple)(struct gpio_chip *gc, 380 unsigned long *mask, 381 unsigned long *bits); 382 void (*set)(struct gpio_chip *gc, 383 unsigned int offset, int value); 384 void (*set_multiple)(struct gpio_chip *gc, 385 unsigned long *mask, 386 unsigned long *bits); 387 int (*set_config)(struct gpio_chip *gc, 388 unsigned int offset, 389 unsigned long config); 390 int (*to_irq)(struct gpio_chip *gc, 391 unsigned int offset); 392 393 void (*dbg_show)(struct seq_file *s, 394 struct gpio_chip *gc); 395 396 int (*init_valid_mask)(struct gpio_chip *gc, 397 unsigned long *valid_mask, 398 unsigned int ngpios); 399 400 int (*add_pin_ranges)(struct gpio_chip *gc); 401 402 int base; 403 u16 ngpio; 404 u16 offset; 405 const char *const *names; 406 bool can_sleep; 407 408 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 409 unsigned long (*read_reg)(void __iomem *reg); 410 void (*write_reg)(void __iomem *reg, unsigned long data); 411 bool be_bits; 412 void __iomem *reg_dat; 413 void __iomem *reg_set; 414 void __iomem *reg_clr; 415 void __iomem *reg_dir_out; 416 void __iomem *reg_dir_in; 417 bool bgpio_dir_unreadable; 418 int bgpio_bits; 419 spinlock_t bgpio_lock; 420 unsigned long bgpio_data; 421 unsigned long bgpio_dir; 422 #endif /* CONFIG_GPIO_GENERIC */ 423 424 #ifdef CONFIG_GPIOLIB_IRQCHIP 425 /* 426 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 427 * to handle IRQs for most practical cases. 428 */ 429 430 /** 431 * @irq: 432 * 433 * Integrates interrupt chip functionality with the GPIO chip. Can be 434 * used to handle IRQs for most practical cases. 435 */ 436 struct gpio_irq_chip irq; 437 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 438 439 /** 440 * @valid_mask: 441 * 442 * If not %NULL, holds bitmask of GPIOs which are valid to be used 443 * from the chip. 444 */ 445 unsigned long *valid_mask; 446 447 #if defined(CONFIG_OF_GPIO) 448 /* 449 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in 450 * the device tree automatically may have an OF translation 451 */ 452 453 /** 454 * @of_node: 455 * 456 * Pointer to a device tree node representing this GPIO controller. 457 */ 458 struct device_node *of_node; 459 460 /** 461 * @of_gpio_n_cells: 462 * 463 * Number of cells used to form the GPIO specifier. 464 */ 465 unsigned int of_gpio_n_cells; 466 467 /** 468 * @of_xlate: 469 * 470 * Callback to translate a device tree GPIO specifier into a chip- 471 * relative GPIO number and flags. 472 */ 473 int (*of_xlate)(struct gpio_chip *gc, 474 const struct of_phandle_args *gpiospec, u32 *flags); 475 #endif /* CONFIG_OF_GPIO */ 476 }; 477 478 extern const char *gpiochip_is_requested(struct gpio_chip *gc, 479 unsigned int offset); 480 481 /** 482 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range 483 * @chip: the chip to query 484 * @i: loop variable 485 * @base: first GPIO in the range 486 * @size: amount of GPIOs to check starting from @base 487 * @label: label of current GPIO 488 */ 489 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \ 490 for (i = 0; i < size; i++) \ 491 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else 492 493 /* Iterates over all requested GPIO of the given @chip */ 494 #define for_each_requested_gpio(chip, i, label) \ 495 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label) 496 497 /* add/remove chips */ 498 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, 499 struct lock_class_key *lock_key, 500 struct lock_class_key *request_key); 501 502 /** 503 * gpiochip_add_data() - register a gpio_chip 504 * @gc: the chip to register, with gc->base initialized 505 * @data: driver-private data associated with this chip 506 * 507 * Context: potentially before irqs will work 508 * 509 * When gpiochip_add_data() is called very early during boot, so that GPIOs 510 * can be freely used, the gc->parent device must be registered before 511 * the gpio framework's arch_initcall(). Otherwise sysfs initialization 512 * for GPIOs will fail rudely. 513 * 514 * gpiochip_add_data() must only be called after gpiolib initialization, 515 * i.e. after core_initcall(). 516 * 517 * If gc->base is negative, this requests dynamic assignment of 518 * a range of valid GPIOs. 519 * 520 * Returns: 521 * A negative errno if the chip can't be registered, such as because the 522 * gc->base is invalid or already associated with a different chip. 523 * Otherwise it returns zero as a success code. 524 */ 525 #ifdef CONFIG_LOCKDEP 526 #define gpiochip_add_data(gc, data) ({ \ 527 static struct lock_class_key lock_key; \ 528 static struct lock_class_key request_key; \ 529 gpiochip_add_data_with_key(gc, data, &lock_key, \ 530 &request_key); \ 531 }) 532 #define devm_gpiochip_add_data(dev, gc, data) ({ \ 533 static struct lock_class_key lock_key; \ 534 static struct lock_class_key request_key; \ 535 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \ 536 &request_key); \ 537 }) 538 #else 539 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL) 540 #define devm_gpiochip_add_data(dev, gc, data) \ 541 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL) 542 #endif /* CONFIG_LOCKDEP */ 543 544 static inline int gpiochip_add(struct gpio_chip *gc) 545 { 546 return gpiochip_add_data(gc, NULL); 547 } 548 extern void gpiochip_remove(struct gpio_chip *gc); 549 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data, 550 struct lock_class_key *lock_key, 551 struct lock_class_key *request_key); 552 553 extern struct gpio_chip *gpiochip_find(void *data, 554 int (*match)(struct gpio_chip *gc, void *data)); 555 556 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset); 557 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset); 558 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset); 559 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset); 560 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); 561 562 /* Line status inquiry for drivers */ 563 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); 564 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); 565 566 /* Sleep persistence inquiry for drivers */ 567 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset); 568 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset); 569 570 /* get driver data */ 571 void *gpiochip_get_data(struct gpio_chip *gc); 572 573 struct bgpio_pdata { 574 const char *label; 575 int base; 576 int ngpio; 577 }; 578 579 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 580 581 void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, 582 unsigned int parent_hwirq, 583 unsigned int parent_type); 584 void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, 585 unsigned int parent_hwirq, 586 unsigned int parent_type); 587 588 #else 589 590 static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, 591 unsigned int parent_hwirq, 592 unsigned int parent_type) 593 { 594 return NULL; 595 } 596 597 static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, 598 unsigned int parent_hwirq, 599 unsigned int parent_type) 600 { 601 return NULL; 602 } 603 604 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ 605 606 int bgpio_init(struct gpio_chip *gc, struct device *dev, 607 unsigned long sz, void __iomem *dat, void __iomem *set, 608 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 609 unsigned long flags); 610 611 #define BGPIOF_BIG_ENDIAN BIT(0) 612 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 613 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 614 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 615 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 616 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 617 #define BGPIOF_NO_SET_ON_INPUT BIT(6) 618 619 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, 620 irq_hw_number_t hwirq); 621 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq); 622 623 int gpiochip_irq_domain_activate(struct irq_domain *domain, 624 struct irq_data *data, bool reserve); 625 void gpiochip_irq_domain_deactivate(struct irq_domain *domain, 626 struct irq_data *data); 627 628 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc, 629 unsigned int offset); 630 631 #ifdef CONFIG_GPIOLIB_IRQCHIP 632 int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 633 struct irq_domain *domain); 634 #else 635 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 636 struct irq_domain *domain) 637 { 638 WARN_ON(1); 639 return -EINVAL; 640 } 641 #endif 642 643 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset); 644 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset); 645 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset, 646 unsigned long config); 647 648 /** 649 * struct gpio_pin_range - pin range controlled by a gpio chip 650 * @node: list for maintaining set of pin ranges, used internally 651 * @pctldev: pinctrl device which handles corresponding pins 652 * @range: actual range of pins controlled by a gpio controller 653 */ 654 struct gpio_pin_range { 655 struct list_head node; 656 struct pinctrl_dev *pctldev; 657 struct pinctrl_gpio_range range; 658 }; 659 660 #ifdef CONFIG_PINCTRL 661 662 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 663 unsigned int gpio_offset, unsigned int pin_offset, 664 unsigned int npins); 665 int gpiochip_add_pingroup_range(struct gpio_chip *gc, 666 struct pinctrl_dev *pctldev, 667 unsigned int gpio_offset, const char *pin_group); 668 void gpiochip_remove_pin_ranges(struct gpio_chip *gc); 669 670 #else /* ! CONFIG_PINCTRL */ 671 672 static inline int 673 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 674 unsigned int gpio_offset, unsigned int pin_offset, 675 unsigned int npins) 676 { 677 return 0; 678 } 679 static inline int 680 gpiochip_add_pingroup_range(struct gpio_chip *gc, 681 struct pinctrl_dev *pctldev, 682 unsigned int gpio_offset, const char *pin_group) 683 { 684 return 0; 685 } 686 687 static inline void 688 gpiochip_remove_pin_ranges(struct gpio_chip *gc) 689 { 690 } 691 692 #endif /* CONFIG_PINCTRL */ 693 694 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc, 695 unsigned int hwnum, 696 const char *label, 697 enum gpio_lookup_flags lflags, 698 enum gpiod_flags dflags); 699 void gpiochip_free_own_desc(struct gpio_desc *desc); 700 701 #ifdef CONFIG_GPIOLIB 702 703 /* lock/unlock as IRQ */ 704 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset); 705 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset); 706 707 708 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 709 710 #else /* CONFIG_GPIOLIB */ 711 712 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 713 { 714 /* GPIO can never have been requested */ 715 WARN_ON(1); 716 return ERR_PTR(-ENODEV); 717 } 718 719 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc, 720 unsigned int offset) 721 { 722 WARN_ON(1); 723 return -EINVAL; 724 } 725 726 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc, 727 unsigned int offset) 728 { 729 WARN_ON(1); 730 } 731 #endif /* CONFIG_GPIOLIB */ 732 733 #endif /* __LINUX_GPIO_DRIVER_H */ 734