1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * FPGA Framework 4 * 5 * Copyright (C) 2013-2016 Altera Corporation 6 * Copyright (C) 2017 Intel Corporation 7 */ 8 #ifndef _LINUX_FPGA_MGR_H 9 #define _LINUX_FPGA_MGR_H 10 11 #include <linux/mutex.h> 12 #include <linux/platform_device.h> 13 14 struct fpga_manager; 15 struct sg_table; 16 17 /** 18 * enum fpga_mgr_states - fpga framework states 19 * @FPGA_MGR_STATE_UNKNOWN: can't determine state 20 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off 21 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up 22 * @FPGA_MGR_STATE_RESET: FPGA in reset state 23 * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress 24 * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed 25 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming 26 * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage 27 * @FPGA_MGR_STATE_WRITE: writing image to FPGA 28 * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA 29 * @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps 30 * @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE 31 * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating 32 */ 33 enum fpga_mgr_states { 34 /* default FPGA states */ 35 FPGA_MGR_STATE_UNKNOWN, 36 FPGA_MGR_STATE_POWER_OFF, 37 FPGA_MGR_STATE_POWER_UP, 38 FPGA_MGR_STATE_RESET, 39 40 /* getting an image for loading */ 41 FPGA_MGR_STATE_FIRMWARE_REQ, 42 FPGA_MGR_STATE_FIRMWARE_REQ_ERR, 43 44 /* write sequence: init, write, complete */ 45 FPGA_MGR_STATE_WRITE_INIT, 46 FPGA_MGR_STATE_WRITE_INIT_ERR, 47 FPGA_MGR_STATE_WRITE, 48 FPGA_MGR_STATE_WRITE_ERR, 49 FPGA_MGR_STATE_WRITE_COMPLETE, 50 FPGA_MGR_STATE_WRITE_COMPLETE_ERR, 51 52 /* fpga is programmed and operating */ 53 FPGA_MGR_STATE_OPERATING, 54 }; 55 56 /* 57 * FPGA Manager flags 58 * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported 59 * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting 60 * FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first 61 * FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed 62 */ 63 #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) 64 #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) 65 #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) 66 #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) 67 #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4) 68 69 /** 70 * struct fpga_image_info - information specific to a FPGA image 71 * @flags: boolean flags as defined above 72 * @enable_timeout_us: maximum time to enable traffic through bridge (uSec) 73 * @disable_timeout_us: maximum time to disable traffic through bridge (uSec) 74 * @config_complete_timeout_us: maximum time for FPGA to switch to operating 75 * status in the write_complete op. 76 * @firmware_name: name of FPGA image firmware file 77 * @sgt: scatter/gather table containing FPGA image 78 * @buf: contiguous buffer containing FPGA image 79 * @count: size of buf 80 * @dev: device that owns this 81 * @overlay: Device Tree overlay 82 */ 83 struct fpga_image_info { 84 u32 flags; 85 u32 enable_timeout_us; 86 u32 disable_timeout_us; 87 u32 config_complete_timeout_us; 88 char *firmware_name; 89 struct sg_table *sgt; 90 const char *buf; 91 size_t count; 92 struct device *dev; 93 #ifdef CONFIG_OF 94 struct device_node *overlay; 95 #endif 96 }; 97 98 /** 99 * struct fpga_manager_ops - ops for low level fpga manager drivers 100 * @initial_header_size: Maximum number of bytes that should be passed into write_init 101 * @state: returns an enum value of the FPGA's state 102 * @write_init: prepare the FPGA to receive confuration data 103 * @write: write count bytes of configuration data to the FPGA 104 * @write_sg: write the scatter list of configuration data to the FPGA 105 * @write_complete: set FPGA to operating state after writing is done 106 * @fpga_remove: optional: Set FPGA into a specific state during driver remove 107 * @groups: optional attribute groups. 108 * 109 * fpga_manager_ops are the low level functions implemented by a specific 110 * fpga manager driver. The optional ones are tested for NULL before being 111 * called, so leaving them out is fine. 112 */ 113 struct fpga_manager_ops { 114 size_t initial_header_size; 115 enum fpga_mgr_states (*state)(struct fpga_manager *mgr); 116 int (*write_init)(struct fpga_manager *mgr, 117 struct fpga_image_info *info, 118 const char *buf, size_t count); 119 int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); 120 int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); 121 int (*write_complete)(struct fpga_manager *mgr, 122 struct fpga_image_info *info); 123 void (*fpga_remove)(struct fpga_manager *mgr); 124 const struct attribute_group **groups; 125 }; 126 127 /** 128 * struct fpga_manager - fpga manager structure 129 * @name: name of low level fpga manager 130 * @dev: fpga manager device 131 * @ref_mutex: only allows one reference to fpga manager 132 * @state: state of fpga manager 133 * @mops: pointer to struct of fpga manager ops 134 * @priv: low level driver private date 135 */ 136 struct fpga_manager { 137 const char *name; 138 struct device dev; 139 struct mutex ref_mutex; 140 enum fpga_mgr_states state; 141 const struct fpga_manager_ops *mops; 142 void *priv; 143 }; 144 145 #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev) 146 147 struct fpga_image_info *fpga_image_info_alloc(struct device *dev); 148 149 void fpga_image_info_free(struct fpga_image_info *info); 150 151 int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info); 152 153 int fpga_mgr_lock(struct fpga_manager *mgr); 154 void fpga_mgr_unlock(struct fpga_manager *mgr); 155 156 struct fpga_manager *of_fpga_mgr_get(struct device_node *node); 157 158 struct fpga_manager *fpga_mgr_get(struct device *dev); 159 160 void fpga_mgr_put(struct fpga_manager *mgr); 161 162 struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name, 163 const struct fpga_manager_ops *mops, 164 void *priv); 165 void fpga_mgr_free(struct fpga_manager *mgr); 166 int fpga_mgr_register(struct fpga_manager *mgr); 167 void fpga_mgr_unregister(struct fpga_manager *mgr); 168 169 #endif /*_LINUX_FPGA_MGR_H */ 170