xref: /openbmc/linux/include/linux/fpga/fpga-mgr.h (revision baa6d396)
16a8c3be7SAlan Tull /*
26a8c3be7SAlan Tull  * FPGA Framework
36a8c3be7SAlan Tull  *
46a8c3be7SAlan Tull  *  Copyright (C) 2013-2015 Altera Corporation
56a8c3be7SAlan Tull  *
66a8c3be7SAlan Tull  * This program is free software; you can redistribute it and/or modify it
76a8c3be7SAlan Tull  * under the terms and conditions of the GNU General Public License,
86a8c3be7SAlan Tull  * version 2, as published by the Free Software Foundation.
96a8c3be7SAlan Tull  *
106a8c3be7SAlan Tull  * This program is distributed in the hope it will be useful, but WITHOUT
116a8c3be7SAlan Tull  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
126a8c3be7SAlan Tull  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
136a8c3be7SAlan Tull  * more details.
146a8c3be7SAlan Tull  *
156a8c3be7SAlan Tull  * You should have received a copy of the GNU General Public License along with
166a8c3be7SAlan Tull  * this program.  If not, see <http://www.gnu.org/licenses/>.
176a8c3be7SAlan Tull  */
186a8c3be7SAlan Tull #include <linux/mutex.h>
196a8c3be7SAlan Tull #include <linux/platform_device.h>
206a8c3be7SAlan Tull 
216a8c3be7SAlan Tull #ifndef _LINUX_FPGA_MGR_H
226a8c3be7SAlan Tull #define _LINUX_FPGA_MGR_H
236a8c3be7SAlan Tull 
246a8c3be7SAlan Tull struct fpga_manager;
25baa6d396SJason Gunthorpe struct sg_table;
266a8c3be7SAlan Tull 
276a8c3be7SAlan Tull /**
286a8c3be7SAlan Tull  * enum fpga_mgr_states - fpga framework states
296a8c3be7SAlan Tull  * @FPGA_MGR_STATE_UNKNOWN: can't determine state
306a8c3be7SAlan Tull  * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
316a8c3be7SAlan Tull  * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
326a8c3be7SAlan Tull  * @FPGA_MGR_STATE_RESET: FPGA in reset state
336a8c3be7SAlan Tull  * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress
346a8c3be7SAlan Tull  * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed
356a8c3be7SAlan Tull  * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
366a8c3be7SAlan Tull  * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
376a8c3be7SAlan Tull  * @FPGA_MGR_STATE_WRITE: writing image to FPGA
386a8c3be7SAlan Tull  * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA
396a8c3be7SAlan Tull  * @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps
406a8c3be7SAlan Tull  * @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
416a8c3be7SAlan Tull  * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating
426a8c3be7SAlan Tull  */
436a8c3be7SAlan Tull enum fpga_mgr_states {
446a8c3be7SAlan Tull 	/* default FPGA states */
456a8c3be7SAlan Tull 	FPGA_MGR_STATE_UNKNOWN,
466a8c3be7SAlan Tull 	FPGA_MGR_STATE_POWER_OFF,
476a8c3be7SAlan Tull 	FPGA_MGR_STATE_POWER_UP,
486a8c3be7SAlan Tull 	FPGA_MGR_STATE_RESET,
496a8c3be7SAlan Tull 
506a8c3be7SAlan Tull 	/* getting an image for loading */
516a8c3be7SAlan Tull 	FPGA_MGR_STATE_FIRMWARE_REQ,
526a8c3be7SAlan Tull 	FPGA_MGR_STATE_FIRMWARE_REQ_ERR,
536a8c3be7SAlan Tull 
546a8c3be7SAlan Tull 	/* write sequence: init, write, complete */
556a8c3be7SAlan Tull 	FPGA_MGR_STATE_WRITE_INIT,
566a8c3be7SAlan Tull 	FPGA_MGR_STATE_WRITE_INIT_ERR,
576a8c3be7SAlan Tull 	FPGA_MGR_STATE_WRITE,
586a8c3be7SAlan Tull 	FPGA_MGR_STATE_WRITE_ERR,
596a8c3be7SAlan Tull 	FPGA_MGR_STATE_WRITE_COMPLETE,
606a8c3be7SAlan Tull 	FPGA_MGR_STATE_WRITE_COMPLETE_ERR,
616a8c3be7SAlan Tull 
626a8c3be7SAlan Tull 	/* fpga is programmed and operating */
636a8c3be7SAlan Tull 	FPGA_MGR_STATE_OPERATING,
646a8c3be7SAlan Tull };
656a8c3be7SAlan Tull 
666a8c3be7SAlan Tull /*
676a8c3be7SAlan Tull  * FPGA Manager flags
686a8c3be7SAlan Tull  * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
690fa20cdfSAlan Tull  * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
706a8c3be7SAlan Tull  */
716a8c3be7SAlan Tull #define FPGA_MGR_PARTIAL_RECONFIG	BIT(0)
720fa20cdfSAlan Tull #define FPGA_MGR_EXTERNAL_CONFIG	BIT(1)
736a8c3be7SAlan Tull 
746a8c3be7SAlan Tull /**
751df2865fSAlan Tull  * struct fpga_image_info - information specific to a FPGA image
761df2865fSAlan Tull  * @flags: boolean flags as defined above
771df2865fSAlan Tull  * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
781df2865fSAlan Tull  * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
791df2865fSAlan Tull  */
801df2865fSAlan Tull struct fpga_image_info {
811df2865fSAlan Tull 	u32 flags;
821df2865fSAlan Tull 	u32 enable_timeout_us;
831df2865fSAlan Tull 	u32 disable_timeout_us;
841df2865fSAlan Tull };
851df2865fSAlan Tull 
861df2865fSAlan Tull /**
876a8c3be7SAlan Tull  * struct fpga_manager_ops - ops for low level fpga manager drivers
881d7f1589SJason Gunthorpe  * @initial_header_size: Maximum number of bytes that should be passed into write_init
896a8c3be7SAlan Tull  * @state: returns an enum value of the FPGA's state
906a8c3be7SAlan Tull  * @write_init: prepare the FPGA to receive confuration data
916a8c3be7SAlan Tull  * @write: write count bytes of configuration data to the FPGA
92baa6d396SJason Gunthorpe  * @write_sg: write the scatter list of configuration data to the FPGA
936a8c3be7SAlan Tull  * @write_complete: set FPGA to operating state after writing is done
946a8c3be7SAlan Tull  * @fpga_remove: optional: Set FPGA into a specific state during driver remove
956a8c3be7SAlan Tull  *
966a8c3be7SAlan Tull  * fpga_manager_ops are the low level functions implemented by a specific
976a8c3be7SAlan Tull  * fpga manager driver.  The optional ones are tested for NULL before being
986a8c3be7SAlan Tull  * called, so leaving them out is fine.
996a8c3be7SAlan Tull  */
1006a8c3be7SAlan Tull struct fpga_manager_ops {
1011d7f1589SJason Gunthorpe 	size_t initial_header_size;
1026a8c3be7SAlan Tull 	enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
1031df2865fSAlan Tull 	int (*write_init)(struct fpga_manager *mgr,
1041df2865fSAlan Tull 			  struct fpga_image_info *info,
1056a8c3be7SAlan Tull 			  const char *buf, size_t count);
1066a8c3be7SAlan Tull 	int (*write)(struct fpga_manager *mgr, const char *buf, size_t count);
107baa6d396SJason Gunthorpe 	int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt);
1081df2865fSAlan Tull 	int (*write_complete)(struct fpga_manager *mgr,
1091df2865fSAlan Tull 			      struct fpga_image_info *info);
1106a8c3be7SAlan Tull 	void (*fpga_remove)(struct fpga_manager *mgr);
1116a8c3be7SAlan Tull };
1126a8c3be7SAlan Tull 
1136a8c3be7SAlan Tull /**
1146a8c3be7SAlan Tull  * struct fpga_manager - fpga manager structure
1156a8c3be7SAlan Tull  * @name: name of low level fpga manager
1166a8c3be7SAlan Tull  * @dev: fpga manager device
1176a8c3be7SAlan Tull  * @ref_mutex: only allows one reference to fpga manager
1186a8c3be7SAlan Tull  * @state: state of fpga manager
1196a8c3be7SAlan Tull  * @mops: pointer to struct of fpga manager ops
1206a8c3be7SAlan Tull  * @priv: low level driver private date
1216a8c3be7SAlan Tull  */
1226a8c3be7SAlan Tull struct fpga_manager {
1236a8c3be7SAlan Tull 	const char *name;
1246a8c3be7SAlan Tull 	struct device dev;
1256a8c3be7SAlan Tull 	struct mutex ref_mutex;
1266a8c3be7SAlan Tull 	enum fpga_mgr_states state;
1276a8c3be7SAlan Tull 	const struct fpga_manager_ops *mops;
1286a8c3be7SAlan Tull 	void *priv;
1296a8c3be7SAlan Tull };
1306a8c3be7SAlan Tull 
1316a8c3be7SAlan Tull #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
1326a8c3be7SAlan Tull 
1331df2865fSAlan Tull int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
1346a8c3be7SAlan Tull 		      const char *buf, size_t count);
135baa6d396SJason Gunthorpe int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, struct fpga_image_info *info,
136baa6d396SJason Gunthorpe 			 struct sg_table *sgt);
1376a8c3be7SAlan Tull 
1381df2865fSAlan Tull int fpga_mgr_firmware_load(struct fpga_manager *mgr,
1391df2865fSAlan Tull 			   struct fpga_image_info *info,
1406a8c3be7SAlan Tull 			   const char *image_name);
1416a8c3be7SAlan Tull 
1426a8c3be7SAlan Tull struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
1436a8c3be7SAlan Tull 
1449dce0287SAlan Tull struct fpga_manager *fpga_mgr_get(struct device *dev);
1459dce0287SAlan Tull 
1466a8c3be7SAlan Tull void fpga_mgr_put(struct fpga_manager *mgr);
1476a8c3be7SAlan Tull 
1486a8c3be7SAlan Tull int fpga_mgr_register(struct device *dev, const char *name,
1496a8c3be7SAlan Tull 		      const struct fpga_manager_ops *mops, void *priv);
1506a8c3be7SAlan Tull 
1516a8c3be7SAlan Tull void fpga_mgr_unregister(struct device *dev);
1526a8c3be7SAlan Tull 
1536a8c3be7SAlan Tull #endif /*_LINUX_FPGA_MGR_H */
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