16a8c3be7SAlan Tull /* 26a8c3be7SAlan Tull * FPGA Framework 36a8c3be7SAlan Tull * 45cf0c7f6SAlan Tull * Copyright (C) 2013-2016 Altera Corporation 55cf0c7f6SAlan Tull * Copyright (C) 2017 Intel Corporation 66a8c3be7SAlan Tull * 76a8c3be7SAlan Tull * This program is free software; you can redistribute it and/or modify it 86a8c3be7SAlan Tull * under the terms and conditions of the GNU General Public License, 96a8c3be7SAlan Tull * version 2, as published by the Free Software Foundation. 106a8c3be7SAlan Tull * 116a8c3be7SAlan Tull * This program is distributed in the hope it will be useful, but WITHOUT 126a8c3be7SAlan Tull * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 136a8c3be7SAlan Tull * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 146a8c3be7SAlan Tull * more details. 156a8c3be7SAlan Tull * 166a8c3be7SAlan Tull * You should have received a copy of the GNU General Public License along with 176a8c3be7SAlan Tull * this program. If not, see <http://www.gnu.org/licenses/>. 186a8c3be7SAlan Tull */ 196a8c3be7SAlan Tull #ifndef _LINUX_FPGA_MGR_H 206a8c3be7SAlan Tull #define _LINUX_FPGA_MGR_H 216a8c3be7SAlan Tull 225cf0c7f6SAlan Tull #include <linux/mutex.h> 235cf0c7f6SAlan Tull #include <linux/platform_device.h> 245cf0c7f6SAlan Tull 256a8c3be7SAlan Tull struct fpga_manager; 26baa6d396SJason Gunthorpe struct sg_table; 276a8c3be7SAlan Tull 286a8c3be7SAlan Tull /** 296a8c3be7SAlan Tull * enum fpga_mgr_states - fpga framework states 306a8c3be7SAlan Tull * @FPGA_MGR_STATE_UNKNOWN: can't determine state 316a8c3be7SAlan Tull * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off 326a8c3be7SAlan Tull * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up 336a8c3be7SAlan Tull * @FPGA_MGR_STATE_RESET: FPGA in reset state 346a8c3be7SAlan Tull * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress 356a8c3be7SAlan Tull * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed 366a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming 376a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage 386a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE: writing image to FPGA 396a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA 406a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps 416a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE 426a8c3be7SAlan Tull * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating 436a8c3be7SAlan Tull */ 446a8c3be7SAlan Tull enum fpga_mgr_states { 456a8c3be7SAlan Tull /* default FPGA states */ 466a8c3be7SAlan Tull FPGA_MGR_STATE_UNKNOWN, 476a8c3be7SAlan Tull FPGA_MGR_STATE_POWER_OFF, 486a8c3be7SAlan Tull FPGA_MGR_STATE_POWER_UP, 496a8c3be7SAlan Tull FPGA_MGR_STATE_RESET, 506a8c3be7SAlan Tull 516a8c3be7SAlan Tull /* getting an image for loading */ 526a8c3be7SAlan Tull FPGA_MGR_STATE_FIRMWARE_REQ, 536a8c3be7SAlan Tull FPGA_MGR_STATE_FIRMWARE_REQ_ERR, 546a8c3be7SAlan Tull 556a8c3be7SAlan Tull /* write sequence: init, write, complete */ 566a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE_INIT, 576a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE_INIT_ERR, 586a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE, 596a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE_ERR, 606a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE_COMPLETE, 616a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE_COMPLETE_ERR, 626a8c3be7SAlan Tull 636a8c3be7SAlan Tull /* fpga is programmed and operating */ 646a8c3be7SAlan Tull FPGA_MGR_STATE_OPERATING, 656a8c3be7SAlan Tull }; 666a8c3be7SAlan Tull 676a8c3be7SAlan Tull /* 686a8c3be7SAlan Tull * FPGA Manager flags 696a8c3be7SAlan Tull * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported 700fa20cdfSAlan Tull * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting 7168f6be65SAnatolij Gustschin * FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first 72b37fa560SAnatolij Gustschin * FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed 736a8c3be7SAlan Tull */ 746a8c3be7SAlan Tull #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) 750fa20cdfSAlan Tull #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) 760f4f0c8fSMoritz Fischer #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) 7768f6be65SAnatolij Gustschin #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) 78b37fa560SAnatolij Gustschin #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4) 796a8c3be7SAlan Tull 806a8c3be7SAlan Tull /** 811df2865fSAlan Tull * struct fpga_image_info - information specific to a FPGA image 821df2865fSAlan Tull * @flags: boolean flags as defined above 831df2865fSAlan Tull * @enable_timeout_us: maximum time to enable traffic through bridge (uSec) 841df2865fSAlan Tull * @disable_timeout_us: maximum time to disable traffic through bridge (uSec) 8542d5ec95SAlan Tull * @config_complete_timeout_us: maximum time for FPGA to switch to operating 8642d5ec95SAlan Tull * status in the write_complete op. 875cf0c7f6SAlan Tull * @firmware_name: name of FPGA image firmware file 885cf0c7f6SAlan Tull * @sgt: scatter/gather table containing FPGA image 895cf0c7f6SAlan Tull * @buf: contiguous buffer containing FPGA image 905cf0c7f6SAlan Tull * @count: size of buf 915cf0c7f6SAlan Tull * @dev: device that owns this 9261c32102SAlan Tull * @overlay: Device Tree overlay 931df2865fSAlan Tull */ 941df2865fSAlan Tull struct fpga_image_info { 951df2865fSAlan Tull u32 flags; 961df2865fSAlan Tull u32 enable_timeout_us; 971df2865fSAlan Tull u32 disable_timeout_us; 9842d5ec95SAlan Tull u32 config_complete_timeout_us; 995cf0c7f6SAlan Tull char *firmware_name; 1005cf0c7f6SAlan Tull struct sg_table *sgt; 1015cf0c7f6SAlan Tull const char *buf; 1025cf0c7f6SAlan Tull size_t count; 1035cf0c7f6SAlan Tull struct device *dev; 10461c32102SAlan Tull #ifdef CONFIG_OF 10561c32102SAlan Tull struct device_node *overlay; 10661c32102SAlan Tull #endif 1071df2865fSAlan Tull }; 1081df2865fSAlan Tull 1091df2865fSAlan Tull /** 1106a8c3be7SAlan Tull * struct fpga_manager_ops - ops for low level fpga manager drivers 1111d7f1589SJason Gunthorpe * @initial_header_size: Maximum number of bytes that should be passed into write_init 1126a8c3be7SAlan Tull * @state: returns an enum value of the FPGA's state 1136a8c3be7SAlan Tull * @write_init: prepare the FPGA to receive confuration data 1146a8c3be7SAlan Tull * @write: write count bytes of configuration data to the FPGA 115baa6d396SJason Gunthorpe * @write_sg: write the scatter list of configuration data to the FPGA 1166a8c3be7SAlan Tull * @write_complete: set FPGA to operating state after writing is done 1176a8c3be7SAlan Tull * @fpga_remove: optional: Set FPGA into a specific state during driver remove 1186a8c3be7SAlan Tull * 1196a8c3be7SAlan Tull * fpga_manager_ops are the low level functions implemented by a specific 1206a8c3be7SAlan Tull * fpga manager driver. The optional ones are tested for NULL before being 1216a8c3be7SAlan Tull * called, so leaving them out is fine. 1226a8c3be7SAlan Tull */ 1236a8c3be7SAlan Tull struct fpga_manager_ops { 1241d7f1589SJason Gunthorpe size_t initial_header_size; 1256a8c3be7SAlan Tull enum fpga_mgr_states (*state)(struct fpga_manager *mgr); 1261df2865fSAlan Tull int (*write_init)(struct fpga_manager *mgr, 1271df2865fSAlan Tull struct fpga_image_info *info, 1286a8c3be7SAlan Tull const char *buf, size_t count); 1296a8c3be7SAlan Tull int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); 130baa6d396SJason Gunthorpe int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); 1311df2865fSAlan Tull int (*write_complete)(struct fpga_manager *mgr, 1321df2865fSAlan Tull struct fpga_image_info *info); 1336a8c3be7SAlan Tull void (*fpga_remove)(struct fpga_manager *mgr); 1346a8c3be7SAlan Tull }; 1356a8c3be7SAlan Tull 1366a8c3be7SAlan Tull /** 1376a8c3be7SAlan Tull * struct fpga_manager - fpga manager structure 1386a8c3be7SAlan Tull * @name: name of low level fpga manager 1396a8c3be7SAlan Tull * @dev: fpga manager device 1406a8c3be7SAlan Tull * @ref_mutex: only allows one reference to fpga manager 1416a8c3be7SAlan Tull * @state: state of fpga manager 1426a8c3be7SAlan Tull * @mops: pointer to struct of fpga manager ops 1436a8c3be7SAlan Tull * @priv: low level driver private date 1446a8c3be7SAlan Tull */ 1456a8c3be7SAlan Tull struct fpga_manager { 1466a8c3be7SAlan Tull const char *name; 1476a8c3be7SAlan Tull struct device dev; 1486a8c3be7SAlan Tull struct mutex ref_mutex; 1496a8c3be7SAlan Tull enum fpga_mgr_states state; 1506a8c3be7SAlan Tull const struct fpga_manager_ops *mops; 1516a8c3be7SAlan Tull void *priv; 1526a8c3be7SAlan Tull }; 1536a8c3be7SAlan Tull 1546a8c3be7SAlan Tull #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev) 1556a8c3be7SAlan Tull 1565cf0c7f6SAlan Tull struct fpga_image_info *fpga_image_info_alloc(struct device *dev); 1576a8c3be7SAlan Tull 1585cf0c7f6SAlan Tull void fpga_image_info_free(struct fpga_image_info *info); 1595cf0c7f6SAlan Tull 1605cf0c7f6SAlan Tull int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info); 1616a8c3be7SAlan Tull 162ebf877a5SAlan Tull int fpga_mgr_lock(struct fpga_manager *mgr); 163ebf877a5SAlan Tull void fpga_mgr_unlock(struct fpga_manager *mgr); 164ebf877a5SAlan Tull 1656a8c3be7SAlan Tull struct fpga_manager *of_fpga_mgr_get(struct device_node *node); 1666a8c3be7SAlan Tull 1679dce0287SAlan Tull struct fpga_manager *fpga_mgr_get(struct device *dev); 1689dce0287SAlan Tull 1696a8c3be7SAlan Tull void fpga_mgr_put(struct fpga_manager *mgr); 1706a8c3be7SAlan Tull 1716a8c3be7SAlan Tull int fpga_mgr_register(struct device *dev, const char *name, 1726a8c3be7SAlan Tull const struct fpga_manager_ops *mops, void *priv); 1736a8c3be7SAlan Tull 1746a8c3be7SAlan Tull void fpga_mgr_unregister(struct device *dev); 1756a8c3be7SAlan Tull 1766a8c3be7SAlan Tull #endif /*_LINUX_FPGA_MGR_H */ 177