16a8c3be7SAlan Tull /* 26a8c3be7SAlan Tull * FPGA Framework 36a8c3be7SAlan Tull * 46a8c3be7SAlan Tull * Copyright (C) 2013-2015 Altera Corporation 56a8c3be7SAlan Tull * 66a8c3be7SAlan Tull * This program is free software; you can redistribute it and/or modify it 76a8c3be7SAlan Tull * under the terms and conditions of the GNU General Public License, 86a8c3be7SAlan Tull * version 2, as published by the Free Software Foundation. 96a8c3be7SAlan Tull * 106a8c3be7SAlan Tull * This program is distributed in the hope it will be useful, but WITHOUT 116a8c3be7SAlan Tull * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 126a8c3be7SAlan Tull * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 136a8c3be7SAlan Tull * more details. 146a8c3be7SAlan Tull * 156a8c3be7SAlan Tull * You should have received a copy of the GNU General Public License along with 166a8c3be7SAlan Tull * this program. If not, see <http://www.gnu.org/licenses/>. 176a8c3be7SAlan Tull */ 186a8c3be7SAlan Tull #include <linux/mutex.h> 196a8c3be7SAlan Tull #include <linux/platform_device.h> 206a8c3be7SAlan Tull 216a8c3be7SAlan Tull #ifndef _LINUX_FPGA_MGR_H 226a8c3be7SAlan Tull #define _LINUX_FPGA_MGR_H 236a8c3be7SAlan Tull 246a8c3be7SAlan Tull struct fpga_manager; 256a8c3be7SAlan Tull 266a8c3be7SAlan Tull /** 276a8c3be7SAlan Tull * enum fpga_mgr_states - fpga framework states 286a8c3be7SAlan Tull * @FPGA_MGR_STATE_UNKNOWN: can't determine state 296a8c3be7SAlan Tull * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off 306a8c3be7SAlan Tull * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up 316a8c3be7SAlan Tull * @FPGA_MGR_STATE_RESET: FPGA in reset state 326a8c3be7SAlan Tull * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress 336a8c3be7SAlan Tull * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed 346a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming 356a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage 366a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE: writing image to FPGA 376a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA 386a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps 396a8c3be7SAlan Tull * @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE 406a8c3be7SAlan Tull * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating 416a8c3be7SAlan Tull */ 426a8c3be7SAlan Tull enum fpga_mgr_states { 436a8c3be7SAlan Tull /* default FPGA states */ 446a8c3be7SAlan Tull FPGA_MGR_STATE_UNKNOWN, 456a8c3be7SAlan Tull FPGA_MGR_STATE_POWER_OFF, 466a8c3be7SAlan Tull FPGA_MGR_STATE_POWER_UP, 476a8c3be7SAlan Tull FPGA_MGR_STATE_RESET, 486a8c3be7SAlan Tull 496a8c3be7SAlan Tull /* getting an image for loading */ 506a8c3be7SAlan Tull FPGA_MGR_STATE_FIRMWARE_REQ, 516a8c3be7SAlan Tull FPGA_MGR_STATE_FIRMWARE_REQ_ERR, 526a8c3be7SAlan Tull 536a8c3be7SAlan Tull /* write sequence: init, write, complete */ 546a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE_INIT, 556a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE_INIT_ERR, 566a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE, 576a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE_ERR, 586a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE_COMPLETE, 596a8c3be7SAlan Tull FPGA_MGR_STATE_WRITE_COMPLETE_ERR, 606a8c3be7SAlan Tull 616a8c3be7SAlan Tull /* fpga is programmed and operating */ 626a8c3be7SAlan Tull FPGA_MGR_STATE_OPERATING, 636a8c3be7SAlan Tull }; 646a8c3be7SAlan Tull 656a8c3be7SAlan Tull /* 666a8c3be7SAlan Tull * FPGA Manager flags 676a8c3be7SAlan Tull * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported 680fa20cdfSAlan Tull * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting 696a8c3be7SAlan Tull */ 706a8c3be7SAlan Tull #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) 710fa20cdfSAlan Tull #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) 726a8c3be7SAlan Tull 736a8c3be7SAlan Tull /** 741df2865fSAlan Tull * struct fpga_image_info - information specific to a FPGA image 751df2865fSAlan Tull * @flags: boolean flags as defined above 761df2865fSAlan Tull * @enable_timeout_us: maximum time to enable traffic through bridge (uSec) 771df2865fSAlan Tull * @disable_timeout_us: maximum time to disable traffic through bridge (uSec) 781df2865fSAlan Tull */ 791df2865fSAlan Tull struct fpga_image_info { 801df2865fSAlan Tull u32 flags; 811df2865fSAlan Tull u32 enable_timeout_us; 821df2865fSAlan Tull u32 disable_timeout_us; 831df2865fSAlan Tull }; 841df2865fSAlan Tull 851df2865fSAlan Tull /** 866a8c3be7SAlan Tull * struct fpga_manager_ops - ops for low level fpga manager drivers 871d7f1589SJason Gunthorpe * @initial_header_size: Maximum number of bytes that should be passed into write_init 886a8c3be7SAlan Tull * @state: returns an enum value of the FPGA's state 896a8c3be7SAlan Tull * @write_init: prepare the FPGA to receive confuration data 906a8c3be7SAlan Tull * @write: write count bytes of configuration data to the FPGA 916a8c3be7SAlan Tull * @write_complete: set FPGA to operating state after writing is done 926a8c3be7SAlan Tull * @fpga_remove: optional: Set FPGA into a specific state during driver remove 936a8c3be7SAlan Tull * 946a8c3be7SAlan Tull * fpga_manager_ops are the low level functions implemented by a specific 956a8c3be7SAlan Tull * fpga manager driver. The optional ones are tested for NULL before being 966a8c3be7SAlan Tull * called, so leaving them out is fine. 976a8c3be7SAlan Tull */ 986a8c3be7SAlan Tull struct fpga_manager_ops { 991d7f1589SJason Gunthorpe size_t initial_header_size; 1006a8c3be7SAlan Tull enum fpga_mgr_states (*state)(struct fpga_manager *mgr); 1011df2865fSAlan Tull int (*write_init)(struct fpga_manager *mgr, 1021df2865fSAlan Tull struct fpga_image_info *info, 1036a8c3be7SAlan Tull const char *buf, size_t count); 1046a8c3be7SAlan Tull int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); 1051df2865fSAlan Tull int (*write_complete)(struct fpga_manager *mgr, 1061df2865fSAlan Tull struct fpga_image_info *info); 1076a8c3be7SAlan Tull void (*fpga_remove)(struct fpga_manager *mgr); 1086a8c3be7SAlan Tull }; 1096a8c3be7SAlan Tull 1106a8c3be7SAlan Tull /** 1116a8c3be7SAlan Tull * struct fpga_manager - fpga manager structure 1126a8c3be7SAlan Tull * @name: name of low level fpga manager 1136a8c3be7SAlan Tull * @dev: fpga manager device 1146a8c3be7SAlan Tull * @ref_mutex: only allows one reference to fpga manager 1156a8c3be7SAlan Tull * @state: state of fpga manager 1166a8c3be7SAlan Tull * @mops: pointer to struct of fpga manager ops 1176a8c3be7SAlan Tull * @priv: low level driver private date 1186a8c3be7SAlan Tull */ 1196a8c3be7SAlan Tull struct fpga_manager { 1206a8c3be7SAlan Tull const char *name; 1216a8c3be7SAlan Tull struct device dev; 1226a8c3be7SAlan Tull struct mutex ref_mutex; 1236a8c3be7SAlan Tull enum fpga_mgr_states state; 1246a8c3be7SAlan Tull const struct fpga_manager_ops *mops; 1256a8c3be7SAlan Tull void *priv; 1266a8c3be7SAlan Tull }; 1276a8c3be7SAlan Tull 1286a8c3be7SAlan Tull #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev) 1296a8c3be7SAlan Tull 1301df2865fSAlan Tull int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info, 1316a8c3be7SAlan Tull const char *buf, size_t count); 1326a8c3be7SAlan Tull 1331df2865fSAlan Tull int fpga_mgr_firmware_load(struct fpga_manager *mgr, 1341df2865fSAlan Tull struct fpga_image_info *info, 1356a8c3be7SAlan Tull const char *image_name); 1366a8c3be7SAlan Tull 1376a8c3be7SAlan Tull struct fpga_manager *of_fpga_mgr_get(struct device_node *node); 1386a8c3be7SAlan Tull 1399dce0287SAlan Tull struct fpga_manager *fpga_mgr_get(struct device *dev); 1409dce0287SAlan Tull 1416a8c3be7SAlan Tull void fpga_mgr_put(struct fpga_manager *mgr); 1426a8c3be7SAlan Tull 1436a8c3be7SAlan Tull int fpga_mgr_register(struct device *dev, const char *name, 1446a8c3be7SAlan Tull const struct fpga_manager_ops *mops, void *priv); 1456a8c3be7SAlan Tull 1466a8c3be7SAlan Tull void fpga_mgr_unregister(struct device *dev); 1476a8c3be7SAlan Tull 1486a8c3be7SAlan Tull #endif /*_LINUX_FPGA_MGR_H */ 149