1d27ac2e0SAlexandru Ardelean /* SPDX-License-Identifier: GPL-2.0 */ 2d27ac2e0SAlexandru Ardelean /* 3d27ac2e0SAlexandru Ardelean * Analog Devices AXI common registers & definitions 4d27ac2e0SAlexandru Ardelean * 5d27ac2e0SAlexandru Ardelean * Copyright 2019 Analog Devices Inc. 6d27ac2e0SAlexandru Ardelean * 7d27ac2e0SAlexandru Ardelean * https://wiki.analog.com/resources/fpga/docs/axi_ip 8d27ac2e0SAlexandru Ardelean * https://wiki.analog.com/resources/fpga/docs/hdl/regmap 9d27ac2e0SAlexandru Ardelean */ 10d27ac2e0SAlexandru Ardelean 11d27ac2e0SAlexandru Ardelean #ifndef ADI_AXI_COMMON_H_ 12d27ac2e0SAlexandru Ardelean #define ADI_AXI_COMMON_H_ 13d27ac2e0SAlexandru Ardelean 14d27ac2e0SAlexandru Ardelean #define ADI_AXI_REG_VERSION 0x0000 15d27ac2e0SAlexandru Ardelean 16d27ac2e0SAlexandru Ardelean #define ADI_AXI_PCORE_VER(major, minor, patch) \ 17d27ac2e0SAlexandru Ardelean (((major) << 16) | ((minor) << 8) | (patch)) 18d27ac2e0SAlexandru Ardelean 1920d5fa48SAlexandru Ardelean #define ADI_AXI_PCORE_VER_MAJOR(version) (((version) >> 16) & 0xff) 2020d5fa48SAlexandru Ardelean #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) 2120d5fa48SAlexandru Ardelean #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) 2220d5fa48SAlexandru Ardelean 23d27ac2e0SAlexandru Ardelean #endif /* ADI_AXI_COMMON_H_ */ 24