1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Xilinx Zynq MPSoC Firmware layer 4 * 5 * Copyright (C) 2014-2019 Xilinx 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * Davorin Mista <davorin.mista@aggios.com> 9 * Jolly Shah <jollys@xilinx.com> 10 * Rajan Vaja <rajanv@xilinx.com> 11 */ 12 13 #ifndef __FIRMWARE_ZYNQMP_H__ 14 #define __FIRMWARE_ZYNQMP_H__ 15 16 #include <linux/err.h> 17 18 #define ZYNQMP_PM_VERSION_MAJOR 1 19 #define ZYNQMP_PM_VERSION_MINOR 0 20 21 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \ 22 ZYNQMP_PM_VERSION_MINOR) 23 24 #define ZYNQMP_TZ_VERSION_MAJOR 1 25 #define ZYNQMP_TZ_VERSION_MINOR 0 26 27 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \ 28 ZYNQMP_TZ_VERSION_MINOR) 29 30 /* SMC SIP service Call Function Identifier Prefix */ 31 #define PM_SIP_SVC 0xC2000000 32 #define PM_GET_TRUSTZONE_VERSION 0xa03 33 #define PM_SET_SUSPEND_MODE 0xa02 34 #define GET_CALLBACK_DATA 0xa01 35 36 /* Number of 32bits values in payload */ 37 #define PAYLOAD_ARG_CNT 4U 38 39 /* Number of arguments for a callback */ 40 #define CB_ARG_CNT 4 41 42 /* Payload size (consists of callback API ID + arguments) */ 43 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1) 44 45 #define ZYNQMP_PM_MAX_QOS 100U 46 47 #define GSS_NUM_REGS (4) 48 49 /* Node capabilities */ 50 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U 51 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U 52 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U 53 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U 54 55 /* 56 * Firmware FPGA Manager flags 57 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration 58 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration 59 */ 60 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U 61 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) 62 63 enum pm_api_id { 64 PM_GET_API_VERSION = 1, 65 PM_SYSTEM_SHUTDOWN = 12, 66 PM_REQUEST_NODE = 13, 67 PM_RELEASE_NODE = 14, 68 PM_SET_REQUIREMENT = 15, 69 PM_RESET_ASSERT = 17, 70 PM_RESET_GET_STATUS = 18, 71 PM_PM_INIT_FINALIZE = 21, 72 PM_FPGA_LOAD = 22, 73 PM_FPGA_GET_STATUS = 23, 74 PM_GET_CHIPID = 24, 75 PM_PINCTRL_REQUEST = 28, 76 PM_PINCTRL_RELEASE = 29, 77 PM_PINCTRL_GET_FUNCTION = 30, 78 PM_PINCTRL_SET_FUNCTION = 31, 79 PM_PINCTRL_CONFIG_PARAM_GET = 32, 80 PM_PINCTRL_CONFIG_PARAM_SET = 33, 81 PM_IOCTL = 34, 82 PM_QUERY_DATA = 35, 83 PM_CLOCK_ENABLE = 36, 84 PM_CLOCK_DISABLE = 37, 85 PM_CLOCK_GETSTATE = 38, 86 PM_CLOCK_SETDIVIDER = 39, 87 PM_CLOCK_GETDIVIDER = 40, 88 PM_CLOCK_SETRATE = 41, 89 PM_CLOCK_GETRATE = 42, 90 PM_CLOCK_SETPARENT = 43, 91 PM_CLOCK_GETPARENT = 44, 92 PM_SECURE_AES = 47, 93 PM_FEATURE_CHECK = 63, 94 }; 95 96 /* PMU-FW return status codes */ 97 enum pm_ret_status { 98 XST_PM_SUCCESS = 0, 99 XST_PM_NO_FEATURE = 19, 100 XST_PM_INTERNAL = 2000, 101 XST_PM_CONFLICT = 2001, 102 XST_PM_NO_ACCESS = 2002, 103 XST_PM_INVALID_NODE = 2003, 104 XST_PM_DOUBLE_REQ = 2004, 105 XST_PM_ABORT_SUSPEND = 2005, 106 XST_PM_MULT_USER = 2008, 107 }; 108 109 enum pm_ioctl_id { 110 IOCTL_SD_DLL_RESET = 6, 111 IOCTL_SET_SD_TAPDELAY = 7, 112 IOCTL_SET_PLL_FRAC_MODE = 8, 113 IOCTL_GET_PLL_FRAC_MODE = 9, 114 IOCTL_SET_PLL_FRAC_DATA = 10, 115 IOCTL_GET_PLL_FRAC_DATA = 11, 116 IOCTL_WRITE_GGS = 12, 117 IOCTL_READ_GGS = 13, 118 IOCTL_WRITE_PGGS = 14, 119 IOCTL_READ_PGGS = 15, 120 /* Set healthy bit value */ 121 IOCTL_SET_BOOT_HEALTH_STATUS = 17, 122 }; 123 124 enum pm_query_id { 125 PM_QID_INVALID = 0, 126 PM_QID_CLOCK_GET_NAME = 1, 127 PM_QID_CLOCK_GET_TOPOLOGY = 2, 128 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3, 129 PM_QID_CLOCK_GET_PARENTS = 4, 130 PM_QID_CLOCK_GET_ATTRIBUTES = 5, 131 PM_QID_PINCTRL_GET_NUM_PINS = 6, 132 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7, 133 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8, 134 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9, 135 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10, 136 PM_QID_PINCTRL_GET_PIN_GROUPS = 11, 137 PM_QID_CLOCK_GET_NUM_CLOCKS = 12, 138 PM_QID_CLOCK_GET_MAX_DIVISOR = 13, 139 }; 140 141 enum zynqmp_pm_reset_action { 142 PM_RESET_ACTION_RELEASE = 0, 143 PM_RESET_ACTION_ASSERT = 1, 144 PM_RESET_ACTION_PULSE = 2, 145 }; 146 147 enum zynqmp_pm_reset { 148 ZYNQMP_PM_RESET_START = 1000, 149 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, 150 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001, 151 ZYNQMP_PM_RESET_PCIE_CTRL = 1002, 152 ZYNQMP_PM_RESET_DP = 1003, 153 ZYNQMP_PM_RESET_SWDT_CRF = 1004, 154 ZYNQMP_PM_RESET_AFI_FM5 = 1005, 155 ZYNQMP_PM_RESET_AFI_FM4 = 1006, 156 ZYNQMP_PM_RESET_AFI_FM3 = 1007, 157 ZYNQMP_PM_RESET_AFI_FM2 = 1008, 158 ZYNQMP_PM_RESET_AFI_FM1 = 1009, 159 ZYNQMP_PM_RESET_AFI_FM0 = 1010, 160 ZYNQMP_PM_RESET_GDMA = 1011, 161 ZYNQMP_PM_RESET_GPU_PP1 = 1012, 162 ZYNQMP_PM_RESET_GPU_PP0 = 1013, 163 ZYNQMP_PM_RESET_GPU = 1014, 164 ZYNQMP_PM_RESET_GT = 1015, 165 ZYNQMP_PM_RESET_SATA = 1016, 166 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017, 167 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018, 168 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019, 169 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020, 170 ZYNQMP_PM_RESET_APU_L2 = 1021, 171 ZYNQMP_PM_RESET_ACPU3 = 1022, 172 ZYNQMP_PM_RESET_ACPU2 = 1023, 173 ZYNQMP_PM_RESET_ACPU1 = 1024, 174 ZYNQMP_PM_RESET_ACPU0 = 1025, 175 ZYNQMP_PM_RESET_DDR = 1026, 176 ZYNQMP_PM_RESET_APM_FPD = 1027, 177 ZYNQMP_PM_RESET_SOFT = 1028, 178 ZYNQMP_PM_RESET_GEM0 = 1029, 179 ZYNQMP_PM_RESET_GEM1 = 1030, 180 ZYNQMP_PM_RESET_GEM2 = 1031, 181 ZYNQMP_PM_RESET_GEM3 = 1032, 182 ZYNQMP_PM_RESET_QSPI = 1033, 183 ZYNQMP_PM_RESET_UART0 = 1034, 184 ZYNQMP_PM_RESET_UART1 = 1035, 185 ZYNQMP_PM_RESET_SPI0 = 1036, 186 ZYNQMP_PM_RESET_SPI1 = 1037, 187 ZYNQMP_PM_RESET_SDIO0 = 1038, 188 ZYNQMP_PM_RESET_SDIO1 = 1039, 189 ZYNQMP_PM_RESET_CAN0 = 1040, 190 ZYNQMP_PM_RESET_CAN1 = 1041, 191 ZYNQMP_PM_RESET_I2C0 = 1042, 192 ZYNQMP_PM_RESET_I2C1 = 1043, 193 ZYNQMP_PM_RESET_TTC0 = 1044, 194 ZYNQMP_PM_RESET_TTC1 = 1045, 195 ZYNQMP_PM_RESET_TTC2 = 1046, 196 ZYNQMP_PM_RESET_TTC3 = 1047, 197 ZYNQMP_PM_RESET_SWDT_CRL = 1048, 198 ZYNQMP_PM_RESET_NAND = 1049, 199 ZYNQMP_PM_RESET_ADMA = 1050, 200 ZYNQMP_PM_RESET_GPIO = 1051, 201 ZYNQMP_PM_RESET_IOU_CC = 1052, 202 ZYNQMP_PM_RESET_TIMESTAMP = 1053, 203 ZYNQMP_PM_RESET_RPU_R50 = 1054, 204 ZYNQMP_PM_RESET_RPU_R51 = 1055, 205 ZYNQMP_PM_RESET_RPU_AMBA = 1056, 206 ZYNQMP_PM_RESET_OCM = 1057, 207 ZYNQMP_PM_RESET_RPU_PGE = 1058, 208 ZYNQMP_PM_RESET_USB0_CORERESET = 1059, 209 ZYNQMP_PM_RESET_USB1_CORERESET = 1060, 210 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061, 211 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062, 212 ZYNQMP_PM_RESET_USB0_APB = 1063, 213 ZYNQMP_PM_RESET_USB1_APB = 1064, 214 ZYNQMP_PM_RESET_IPI = 1065, 215 ZYNQMP_PM_RESET_APM_LPD = 1066, 216 ZYNQMP_PM_RESET_RTC = 1067, 217 ZYNQMP_PM_RESET_SYSMON = 1068, 218 ZYNQMP_PM_RESET_AFI_FM6 = 1069, 219 ZYNQMP_PM_RESET_LPD_SWDT = 1070, 220 ZYNQMP_PM_RESET_FPD = 1071, 221 ZYNQMP_PM_RESET_RPU_DBG1 = 1072, 222 ZYNQMP_PM_RESET_RPU_DBG0 = 1073, 223 ZYNQMP_PM_RESET_DBG_LPD = 1074, 224 ZYNQMP_PM_RESET_DBG_FPD = 1075, 225 ZYNQMP_PM_RESET_APLL = 1076, 226 ZYNQMP_PM_RESET_DPLL = 1077, 227 ZYNQMP_PM_RESET_VPLL = 1078, 228 ZYNQMP_PM_RESET_IOPLL = 1079, 229 ZYNQMP_PM_RESET_RPLL = 1080, 230 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081, 231 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082, 232 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083, 233 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084, 234 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085, 235 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086, 236 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087, 237 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088, 238 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089, 239 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090, 240 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091, 241 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092, 242 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093, 243 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094, 244 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095, 245 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096, 246 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097, 247 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098, 248 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099, 249 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100, 250 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101, 251 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102, 252 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103, 253 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104, 254 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105, 255 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106, 256 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107, 257 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108, 258 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109, 259 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110, 260 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111, 261 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112, 262 ZYNQMP_PM_RESET_RPU_LS = 1113, 263 ZYNQMP_PM_RESET_PS_ONLY = 1114, 264 ZYNQMP_PM_RESET_PL = 1115, 265 ZYNQMP_PM_RESET_PS_PL0 = 1116, 266 ZYNQMP_PM_RESET_PS_PL1 = 1117, 267 ZYNQMP_PM_RESET_PS_PL2 = 1118, 268 ZYNQMP_PM_RESET_PS_PL3 = 1119, 269 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 270 }; 271 272 enum zynqmp_pm_suspend_reason { 273 SUSPEND_POWER_REQUEST = 201, 274 SUSPEND_ALERT = 202, 275 SUSPEND_SYSTEM_SHUTDOWN = 203, 276 }; 277 278 enum zynqmp_pm_request_ack { 279 ZYNQMP_PM_REQUEST_ACK_NO = 1, 280 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2, 281 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3, 282 }; 283 284 enum pm_node_id { 285 NODE_SD_0 = 39, 286 NODE_SD_1 = 40, 287 }; 288 289 enum tap_delay_type { 290 PM_TAPDELAY_INPUT = 0, 291 PM_TAPDELAY_OUTPUT = 1, 292 }; 293 294 enum dll_reset_type { 295 PM_DLL_RESET_ASSERT = 0, 296 PM_DLL_RESET_RELEASE = 1, 297 PM_DLL_RESET_PULSE = 2, 298 }; 299 300 enum pm_pinctrl_config_param { 301 PM_PINCTRL_CONFIG_SLEW_RATE = 0, 302 PM_PINCTRL_CONFIG_BIAS_STATUS = 1, 303 PM_PINCTRL_CONFIG_PULL_CTRL = 2, 304 PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3, 305 PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4, 306 PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5, 307 PM_PINCTRL_CONFIG_TRI_STATE = 6, 308 PM_PINCTRL_CONFIG_MAX = 7, 309 }; 310 311 enum pm_pinctrl_slew_rate { 312 PM_PINCTRL_SLEW_RATE_FAST = 0, 313 PM_PINCTRL_SLEW_RATE_SLOW = 1, 314 }; 315 316 enum pm_pinctrl_bias_status { 317 PM_PINCTRL_BIAS_DISABLE = 0, 318 PM_PINCTRL_BIAS_ENABLE = 1, 319 }; 320 321 enum pm_pinctrl_pull_ctrl { 322 PM_PINCTRL_BIAS_PULL_DOWN = 0, 323 PM_PINCTRL_BIAS_PULL_UP = 1, 324 }; 325 326 enum pm_pinctrl_schmitt_cmos { 327 PM_PINCTRL_INPUT_TYPE_CMOS = 0, 328 PM_PINCTRL_INPUT_TYPE_SCHMITT = 1, 329 }; 330 331 enum pm_pinctrl_drive_strength { 332 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0, 333 PM_PINCTRL_DRIVE_STRENGTH_4MA = 1, 334 PM_PINCTRL_DRIVE_STRENGTH_8MA = 2, 335 PM_PINCTRL_DRIVE_STRENGTH_12MA = 3, 336 }; 337 338 enum zynqmp_pm_shutdown_type { 339 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0, 340 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1, 341 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2, 342 }; 343 344 enum zynqmp_pm_shutdown_subtype { 345 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0, 346 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1, 347 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2, 348 }; 349 350 /** 351 * struct zynqmp_pm_query_data - PM query data 352 * @qid: query ID 353 * @arg1: Argument 1 of query data 354 * @arg2: Argument 2 of query data 355 * @arg3: Argument 3 of query data 356 */ 357 struct zynqmp_pm_query_data { 358 u32 qid; 359 u32 arg1; 360 u32 arg2; 361 u32 arg3; 362 }; 363 364 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, 365 u32 arg2, u32 arg3, u32 *ret_payload); 366 367 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) 368 int zynqmp_pm_get_api_version(u32 *version); 369 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version); 370 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); 371 int zynqmp_pm_clock_enable(u32 clock_id); 372 int zynqmp_pm_clock_disable(u32 clock_id); 373 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); 374 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); 375 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); 376 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate); 377 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate); 378 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id); 379 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id); 380 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode); 381 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode); 382 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data); 383 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data); 384 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value); 385 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); 386 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, 387 const enum zynqmp_pm_reset_action assert_flag); 388 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status); 389 int zynqmp_pm_init_finalize(void); 390 int zynqmp_pm_set_suspend_mode(u32 mode); 391 int zynqmp_pm_request_node(const u32 node, const u32 capabilities, 392 const u32 qos, const enum zynqmp_pm_request_ack ack); 393 int zynqmp_pm_release_node(const u32 node); 394 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, 395 const u32 qos, 396 const enum zynqmp_pm_request_ack ack); 397 int zynqmp_pm_aes_engine(const u64 address, u32 *out); 398 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); 399 int zynqmp_pm_fpga_get_status(u32 *value); 400 int zynqmp_pm_write_ggs(u32 index, u32 value); 401 int zynqmp_pm_read_ggs(u32 index, u32 *value); 402 int zynqmp_pm_write_pggs(u32 index, u32 value); 403 int zynqmp_pm_read_pggs(u32 index, u32 *value); 404 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); 405 int zynqmp_pm_set_boot_health_status(u32 value); 406 int zynqmp_pm_pinctrl_request(const u32 pin); 407 int zynqmp_pm_pinctrl_release(const u32 pin); 408 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id); 409 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id); 410 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, 411 u32 *value); 412 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, 413 u32 value); 414 #else 415 static inline int zynqmp_pm_get_api_version(u32 *version) 416 { 417 return -ENODEV; 418 } 419 420 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) 421 { 422 return -ENODEV; 423 } 424 425 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, 426 u32 *out) 427 { 428 return -ENODEV; 429 } 430 431 static inline int zynqmp_pm_clock_enable(u32 clock_id) 432 { 433 return -ENODEV; 434 } 435 436 static inline int zynqmp_pm_clock_disable(u32 clock_id) 437 { 438 return -ENODEV; 439 } 440 441 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) 442 { 443 return -ENODEV; 444 } 445 446 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) 447 { 448 return -ENODEV; 449 } 450 451 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) 452 { 453 return -ENODEV; 454 } 455 456 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) 457 { 458 return -ENODEV; 459 } 460 461 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) 462 { 463 return -ENODEV; 464 } 465 466 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) 467 { 468 return -ENODEV; 469 } 470 471 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) 472 { 473 return -ENODEV; 474 } 475 476 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) 477 { 478 return -ENODEV; 479 } 480 481 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) 482 { 483 return -ENODEV; 484 } 485 486 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) 487 { 488 return -ENODEV; 489 } 490 491 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) 492 { 493 return -ENODEV; 494 } 495 496 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) 497 { 498 return -ENODEV; 499 } 500 501 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) 502 { 503 return -ENODEV; 504 } 505 506 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, 507 const enum zynqmp_pm_reset_action assert_flag) 508 { 509 return -ENODEV; 510 } 511 512 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, 513 u32 *status) 514 { 515 return -ENODEV; 516 } 517 518 static inline int zynqmp_pm_init_finalize(void) 519 { 520 return -ENODEV; 521 } 522 523 static inline int zynqmp_pm_set_suspend_mode(u32 mode) 524 { 525 return -ENODEV; 526 } 527 528 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities, 529 const u32 qos, 530 const enum zynqmp_pm_request_ack ack) 531 { 532 return -ENODEV; 533 } 534 535 static inline int zynqmp_pm_release_node(const u32 node) 536 { 537 return -ENODEV; 538 } 539 540 static inline int zynqmp_pm_set_requirement(const u32 node, 541 const u32 capabilities, 542 const u32 qos, 543 const enum zynqmp_pm_request_ack ack) 544 { 545 return -ENODEV; 546 } 547 548 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) 549 { 550 return -ENODEV; 551 } 552 553 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, 554 const u32 flags) 555 { 556 return -ENODEV; 557 } 558 559 static inline int zynqmp_pm_fpga_get_status(u32 *value) 560 { 561 return -ENODEV; 562 } 563 564 static inline int zynqmp_pm_write_ggs(u32 index, u32 value) 565 { 566 return -ENODEV; 567 } 568 569 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value) 570 { 571 return -ENODEV; 572 } 573 574 static inline int zynqmp_pm_write_pggs(u32 index, u32 value) 575 { 576 return -ENODEV; 577 } 578 579 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) 580 { 581 return -ENODEV; 582 } 583 584 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) 585 { 586 return -ENODEV; 587 } 588 589 static inline int zynqmp_pm_set_boot_health_status(u32 value) 590 { 591 return -ENODEV; 592 } 593 594 static inline int zynqmp_pm_pinctrl_request(const u32 pin) 595 { 596 return -ENODEV; 597 } 598 599 static inline int zynqmp_pm_pinctrl_release(const u32 pin) 600 { 601 return -ENODEV; 602 } 603 604 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id) 605 { 606 return -ENODEV; 607 } 608 609 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id) 610 { 611 return -ENODEV; 612 } 613 614 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, 615 u32 *value) 616 { 617 return -ENODEV; 618 } 619 620 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, 621 u32 value) 622 { 623 return -ENODEV; 624 } 625 #endif 626 627 #endif /* __FIRMWARE_ZYNQMP_H__ */ 628