1 /* 2 * Generic EDAC defs 3 * 4 * Author: Dave Jiang <djiang@mvista.com> 5 * 6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 * 11 */ 12 #ifndef _LINUX_EDAC_H_ 13 #define _LINUX_EDAC_H_ 14 15 #include <linux/atomic.h> 16 #include <linux/device.h> 17 #include <linux/completion.h> 18 #include <linux/workqueue.h> 19 #include <linux/debugfs.h> 20 #include <linux/numa.h> 21 22 #define EDAC_DEVICE_NAME_LEN 31 23 24 struct device; 25 26 #define EDAC_OPSTATE_INVAL -1 27 #define EDAC_OPSTATE_POLL 0 28 #define EDAC_OPSTATE_NMI 1 29 #define EDAC_OPSTATE_INT 2 30 31 extern int edac_op_state; 32 33 struct bus_type *edac_get_sysfs_subsys(void); 34 35 static inline void opstate_init(void) 36 { 37 switch (edac_op_state) { 38 case EDAC_OPSTATE_POLL: 39 case EDAC_OPSTATE_NMI: 40 break; 41 default: 42 edac_op_state = EDAC_OPSTATE_POLL; 43 } 44 return; 45 } 46 47 /* Max length of a DIMM label*/ 48 #define EDAC_MC_LABEL_LEN 31 49 50 /* Maximum size of the location string */ 51 #define LOCATION_SIZE 256 52 53 /* Defines the maximum number of labels that can be reported */ 54 #define EDAC_MAX_LABELS 8 55 56 /* String used to join two or more labels */ 57 #define OTHER_LABEL " or " 58 59 /** 60 * enum dev_type - describe the type of memory DRAM chips used at the stick 61 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it 62 * @DEV_X1: 1 bit for data 63 * @DEV_X2: 2 bits for data 64 * @DEV_X4: 4 bits for data 65 * @DEV_X8: 8 bits for data 66 * @DEV_X16: 16 bits for data 67 * @DEV_X32: 32 bits for data 68 * @DEV_X64: 64 bits for data 69 * 70 * Typical values are x4 and x8. 71 */ 72 enum dev_type { 73 DEV_UNKNOWN = 0, 74 DEV_X1, 75 DEV_X2, 76 DEV_X4, 77 DEV_X8, 78 DEV_X16, 79 DEV_X32, /* Do these parts exist? */ 80 DEV_X64 /* Do these parts exist? */ 81 }; 82 83 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) 84 #define DEV_FLAG_X1 BIT(DEV_X1) 85 #define DEV_FLAG_X2 BIT(DEV_X2) 86 #define DEV_FLAG_X4 BIT(DEV_X4) 87 #define DEV_FLAG_X8 BIT(DEV_X8) 88 #define DEV_FLAG_X16 BIT(DEV_X16) 89 #define DEV_FLAG_X32 BIT(DEV_X32) 90 #define DEV_FLAG_X64 BIT(DEV_X64) 91 92 /** 93 * enum hw_event_mc_err_type - type of the detected error 94 * 95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC 96 * corrected error was detected 97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that 98 * can't be corrected by ECC, but it is not 99 * fatal (maybe it is on an unused memory area, 100 * or the memory controller could recover from 101 * it for example, by re-trying the operation). 102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable 103 * error whose handling is not urgent. This could 104 * be due to hardware data poisoning where the 105 * system can continue operation until the poisoned 106 * data is consumed. Preemptive measures may also 107 * be taken, e.g. offlining pages, etc. 108 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not 109 * be recovered. 110 * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth 111 * type of error: informational logs. 112 */ 113 enum hw_event_mc_err_type { 114 HW_EVENT_ERR_CORRECTED, 115 HW_EVENT_ERR_UNCORRECTED, 116 HW_EVENT_ERR_DEFERRED, 117 HW_EVENT_ERR_FATAL, 118 HW_EVENT_ERR_INFO, 119 }; 120 121 static inline char *mc_event_error_type(const unsigned int err_type) 122 { 123 switch (err_type) { 124 case HW_EVENT_ERR_CORRECTED: 125 return "Corrected"; 126 case HW_EVENT_ERR_UNCORRECTED: 127 return "Uncorrected"; 128 case HW_EVENT_ERR_DEFERRED: 129 return "Deferred"; 130 case HW_EVENT_ERR_FATAL: 131 return "Fatal"; 132 default: 133 case HW_EVENT_ERR_INFO: 134 return "Info"; 135 } 136 } 137 138 /** 139 * enum mem_type - memory types. For a more detailed reference, please see 140 * http://en.wikipedia.org/wiki/DRAM 141 * 142 * @MEM_EMPTY: Empty csrow 143 * @MEM_RESERVED: Reserved csrow type 144 * @MEM_UNKNOWN: Unknown csrow type 145 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995. 146 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998. 147 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant. 148 * @MEM_SDR: SDR - Single data rate SDRAM 149 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory 150 * They use 3 pins for chip select: Pins 0 and 2 are 151 * for rank 0; pins 1 and 3 are for rank 1, if the memory 152 * is dual-rank. 153 * @MEM_RDR: Registered SDR SDRAM 154 * @MEM_DDR: Double data rate SDRAM 155 * http://en.wikipedia.org/wiki/DDR_SDRAM 156 * @MEM_RDDR: Registered Double data rate SDRAM 157 * This is a variant of the DDR memories. 158 * A registered memory has a buffer inside it, hiding 159 * part of the memory details to the memory controller. 160 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers. 161 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. 162 * Those memories are labeled as "PC2-" instead of "PC" to 163 * differentiate from DDR. 164 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205 165 * and JESD206. 166 * Those memories are accessed per DIMM slot, and not by 167 * a chip select signal. 168 * @MEM_RDDR2: Registered DDR2 RAM 169 * This is a variant of the DDR2 memories. 170 * @MEM_XDR: Rambus XDR 171 * It is an evolution of the original RAMBUS memories, 172 * created to compete with DDR2. Weren't used on any 173 * x86 arch, but cell_edac PPC memory controller uses it. 174 * @MEM_DDR3: DDR3 RAM 175 * @MEM_RDDR3: Registered DDR3 RAM 176 * This is a variant of the DDR3 memories. 177 * @MEM_LRDDR3: Load-Reduced DDR3 memory. 178 * @MEM_DDR4: Unbuffered DDR4 RAM 179 * @MEM_RDDR4: Registered DDR4 RAM 180 * This is a variant of the DDR4 memories. 181 * @MEM_LRDDR4: Load-Reduced DDR4 memory. 182 * @MEM_NVDIMM: Non-volatile RAM 183 */ 184 enum mem_type { 185 MEM_EMPTY = 0, 186 MEM_RESERVED, 187 MEM_UNKNOWN, 188 MEM_FPM, 189 MEM_EDO, 190 MEM_BEDO, 191 MEM_SDR, 192 MEM_RDR, 193 MEM_DDR, 194 MEM_RDDR, 195 MEM_RMBS, 196 MEM_DDR2, 197 MEM_FB_DDR2, 198 MEM_RDDR2, 199 MEM_XDR, 200 MEM_DDR3, 201 MEM_RDDR3, 202 MEM_LRDDR3, 203 MEM_DDR4, 204 MEM_RDDR4, 205 MEM_LRDDR4, 206 MEM_NVDIMM, 207 }; 208 209 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) 210 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED) 211 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) 212 #define MEM_FLAG_FPM BIT(MEM_FPM) 213 #define MEM_FLAG_EDO BIT(MEM_EDO) 214 #define MEM_FLAG_BEDO BIT(MEM_BEDO) 215 #define MEM_FLAG_SDR BIT(MEM_SDR) 216 #define MEM_FLAG_RDR BIT(MEM_RDR) 217 #define MEM_FLAG_DDR BIT(MEM_DDR) 218 #define MEM_FLAG_RDDR BIT(MEM_RDDR) 219 #define MEM_FLAG_RMBS BIT(MEM_RMBS) 220 #define MEM_FLAG_DDR2 BIT(MEM_DDR2) 221 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) 222 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) 223 #define MEM_FLAG_XDR BIT(MEM_XDR) 224 #define MEM_FLAG_DDR3 BIT(MEM_DDR3) 225 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) 226 #define MEM_FLAG_DDR4 BIT(MEM_DDR4) 227 #define MEM_FLAG_RDDR4 BIT(MEM_RDDR4) 228 #define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4) 229 #define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM) 230 231 /** 232 * enum edac-type - Error Detection and Correction capabilities and mode 233 * @EDAC_UNKNOWN: Unknown if ECC is available 234 * @EDAC_NONE: Doesn't support ECC 235 * @EDAC_RESERVED: Reserved ECC type 236 * @EDAC_PARITY: Detects parity errors 237 * @EDAC_EC: Error Checking - no correction 238 * @EDAC_SECDED: Single bit error correction, Double detection 239 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist? 240 * @EDAC_S4ECD4ED: Chipkill x4 devices 241 * @EDAC_S8ECD8ED: Chipkill x8 devices 242 * @EDAC_S16ECD16ED: Chipkill x16 devices 243 */ 244 enum edac_type { 245 EDAC_UNKNOWN = 0, 246 EDAC_NONE, 247 EDAC_RESERVED, 248 EDAC_PARITY, 249 EDAC_EC, 250 EDAC_SECDED, 251 EDAC_S2ECD2ED, 252 EDAC_S4ECD4ED, 253 EDAC_S8ECD8ED, 254 EDAC_S16ECD16ED, 255 }; 256 257 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) 258 #define EDAC_FLAG_NONE BIT(EDAC_NONE) 259 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY) 260 #define EDAC_FLAG_EC BIT(EDAC_EC) 261 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED) 262 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) 263 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) 264 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) 265 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) 266 267 /** 268 * enum scrub_type - scrubbing capabilities 269 * @SCRUB_UNKNOWN: Unknown if scrubber is available 270 * @SCRUB_NONE: No scrubber 271 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing 272 * @SCRUB_SW_SRC: Software scrub only errors 273 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error 274 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable 275 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing 276 * @SCRUB_HW_SRC: Hardware scrub only errors 277 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error 278 * @SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable 279 */ 280 enum scrub_type { 281 SCRUB_UNKNOWN = 0, 282 SCRUB_NONE, 283 SCRUB_SW_PROG, 284 SCRUB_SW_SRC, 285 SCRUB_SW_PROG_SRC, 286 SCRUB_SW_TUNABLE, 287 SCRUB_HW_PROG, 288 SCRUB_HW_SRC, 289 SCRUB_HW_PROG_SRC, 290 SCRUB_HW_TUNABLE 291 }; 292 293 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) 294 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) 295 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) 296 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) 297 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) 298 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) 299 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) 300 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) 301 302 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ 303 304 /* EDAC internal operation states */ 305 #define OP_ALLOC 0x100 306 #define OP_RUNNING_POLL 0x201 307 #define OP_RUNNING_INTERRUPT 0x202 308 #define OP_RUNNING_POLL_INTR 0x203 309 #define OP_OFFLINE 0x300 310 311 /** 312 * enum edac_mc_layer - memory controller hierarchy layer 313 * 314 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch" 315 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel" 316 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot" 317 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select" 318 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped 319 * as a single memory area. This is used when 320 * retrieving errors from a firmware driven driver. 321 * 322 * This enum is used by the drivers to tell edac_mc_sysfs what name should 323 * be used when describing a memory stick location. 324 */ 325 enum edac_mc_layer_type { 326 EDAC_MC_LAYER_BRANCH, 327 EDAC_MC_LAYER_CHANNEL, 328 EDAC_MC_LAYER_SLOT, 329 EDAC_MC_LAYER_CHIP_SELECT, 330 EDAC_MC_LAYER_ALL_MEM, 331 }; 332 333 /** 334 * struct edac_mc_layer - describes the memory controller hierarchy 335 * @type: layer type 336 * @size: number of components per layer. For example, 337 * if the channel layer has two channels, size = 2 338 * @is_virt_csrow: This layer is part of the "csrow" when old API 339 * compatibility mode is enabled. Otherwise, it is 340 * a channel 341 */ 342 struct edac_mc_layer { 343 enum edac_mc_layer_type type; 344 unsigned size; 345 bool is_virt_csrow; 346 }; 347 348 /* 349 * Maximum number of layers used by the memory controller to uniquely 350 * identify a single memory stick. 351 * NOTE: Changing this constant requires not only to change the constant 352 * below, but also to change the existing code at the core, as there are 353 * some code there that are optimized for 3 layers. 354 */ 355 #define EDAC_MAX_LAYERS 3 356 357 struct dimm_info { 358 struct device dev; 359 360 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ 361 362 /* Memory location data */ 363 unsigned int location[EDAC_MAX_LAYERS]; 364 365 struct mem_ctl_info *mci; /* the parent */ 366 unsigned int idx; /* index within the parent dimm array */ 367 368 u32 grain; /* granularity of reported error in bytes */ 369 enum dev_type dtype; /* memory device type */ 370 enum mem_type mtype; /* memory dimm type */ 371 enum edac_type edac_mode; /* EDAC mode for this dimm */ 372 373 u32 nr_pages; /* number of pages on this dimm */ 374 375 unsigned int csrow, cschannel; /* Points to the old API data */ 376 377 u16 smbios_handle; /* Handle for SMBIOS type 17 */ 378 379 u32 ce_count; 380 u32 ue_count; 381 }; 382 383 /** 384 * struct rank_info - contains the information for one DIMM rank 385 * 386 * @chan_idx: channel number where the rank is (typically, 0 or 1) 387 * @ce_count: number of correctable errors for this rank 388 * @csrow: A pointer to the chip select row structure (the parent 389 * structure). The location of the rank is given by 390 * the (csrow->csrow_idx, chan_idx) vector. 391 * @dimm: A pointer to the DIMM structure, where the DIMM label 392 * information is stored. 393 * 394 * FIXME: Currently, the EDAC core model will assume one DIMM per rank. 395 * This is a bad assumption, but it makes this patch easier. Later 396 * patches in this series will fix this issue. 397 */ 398 struct rank_info { 399 int chan_idx; 400 struct csrow_info *csrow; 401 struct dimm_info *dimm; 402 403 u32 ce_count; /* Correctable Errors for this csrow */ 404 }; 405 406 struct csrow_info { 407 struct device dev; 408 409 /* Used only by edac_mc_find_csrow_by_page() */ 410 unsigned long first_page; /* first page number in csrow */ 411 unsigned long last_page; /* last page number in csrow */ 412 unsigned long page_mask; /* used for interleaving - 413 * 0UL for non intlv */ 414 415 int csrow_idx; /* the chip-select row */ 416 417 u32 ue_count; /* Uncorrectable Errors for this csrow */ 418 u32 ce_count; /* Correctable Errors for this csrow */ 419 420 struct mem_ctl_info *mci; /* the parent */ 421 422 /* channel information for this csrow */ 423 u32 nr_channels; 424 struct rank_info **channels; 425 }; 426 427 /* 428 * struct errcount_attribute - used to store the several error counts 429 */ 430 struct errcount_attribute_data { 431 int n_layers; 432 int pos[EDAC_MAX_LAYERS]; 433 int layer0, layer1, layer2; 434 }; 435 436 /** 437 * struct edac_raw_error_desc - Raw error report structure 438 * @grain: minimum granularity for an error report, in bytes 439 * @error_count: number of errors of the same type 440 * @type: severity of the error (CE/UE/Fatal) 441 * @top_layer: top layer of the error (layer[0]) 442 * @mid_layer: middle layer of the error (layer[1]) 443 * @low_layer: low layer of the error (layer[2]) 444 * @page_frame_number: page where the error happened 445 * @offset_in_page: page offset 446 * @syndrome: syndrome of the error (or 0 if unknown or if 447 * the syndrome is not applicable) 448 * @msg: error message 449 * @location: location of the error 450 * @label: label of the affected DIMM(s) 451 * @other_detail: other driver-specific detail about the error 452 */ 453 struct edac_raw_error_desc { 454 char location[LOCATION_SIZE]; 455 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS]; 456 long grain; 457 458 u16 error_count; 459 enum hw_event_mc_err_type type; 460 int top_layer; 461 int mid_layer; 462 int low_layer; 463 unsigned long page_frame_number; 464 unsigned long offset_in_page; 465 unsigned long syndrome; 466 const char *msg; 467 const char *other_detail; 468 }; 469 470 /* MEMORY controller information structure 471 */ 472 struct mem_ctl_info { 473 struct device dev; 474 struct bus_type *bus; 475 476 struct list_head link; /* for global list of mem_ctl_info structs */ 477 478 struct module *owner; /* Module owner of this control struct */ 479 480 unsigned long mtype_cap; /* memory types supported by mc */ 481 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ 482 unsigned long edac_cap; /* configuration capabilities - this is 483 * closely related to edac_ctl_cap. The 484 * difference is that the controller may be 485 * capable of s4ecd4ed which would be listed 486 * in edac_ctl_cap, but if channels aren't 487 * capable of s4ecd4ed then the edac_cap would 488 * not have that capability. 489 */ 490 unsigned long scrub_cap; /* chipset scrub capabilities */ 491 enum scrub_type scrub_mode; /* current scrub mode */ 492 493 /* Translates sdram memory scrub rate given in bytes/sec to the 494 internal representation and configures whatever else needs 495 to be configured. 496 */ 497 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw); 498 499 /* Get the current sdram memory scrub rate from the internal 500 representation and converts it to the closest matching 501 bandwidth in bytes/sec. 502 */ 503 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci); 504 505 506 /* pointer to edac checking routine */ 507 void (*edac_check) (struct mem_ctl_info * mci); 508 509 /* 510 * Remaps memory pages: controller pages to physical pages. 511 * For most MC's, this will be NULL. 512 */ 513 /* FIXME - why not send the phys page to begin with? */ 514 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, 515 unsigned long page); 516 int mc_idx; 517 struct csrow_info **csrows; 518 unsigned int nr_csrows, num_cschannel; 519 520 /* 521 * Memory Controller hierarchy 522 * 523 * There are basically two types of memory controller: the ones that 524 * sees memory sticks ("dimms"), and the ones that sees memory ranks. 525 * All old memory controllers enumerate memories per rank, but most 526 * of the recent drivers enumerate memories per DIMM, instead. 527 * When the memory controller is per rank, csbased is true. 528 */ 529 unsigned int n_layers; 530 struct edac_mc_layer *layers; 531 bool csbased; 532 533 /* 534 * DIMM info. Will eventually remove the entire csrows_info some day 535 */ 536 unsigned int tot_dimms; 537 struct dimm_info **dimms; 538 539 /* 540 * FIXME - what about controllers on other busses? - IDs must be 541 * unique. dev pointer should be sufficiently unique, but 542 * BUS:SLOT.FUNC numbers may not be unique. 543 */ 544 struct device *pdev; 545 const char *mod_name; 546 const char *ctl_name; 547 const char *dev_name; 548 void *pvt_info; 549 unsigned long start_time; /* mci load start time (in jiffies) */ 550 551 /* 552 * drivers shouldn't access those fields directly, as the core 553 * already handles that. 554 */ 555 u32 ce_noinfo_count, ue_noinfo_count; 556 u32 ue_mc, ce_mc; 557 558 struct completion complete; 559 560 /* Additional top controller level attributes, but specified 561 * by the low level driver. 562 * 563 * Set by the low level driver to provide attributes at the 564 * controller level. 565 * An array of structures, NULL terminated 566 * 567 * If attributes are desired, then set to array of attributes 568 * If no attributes are desired, leave NULL 569 */ 570 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes; 571 572 /* work struct for this MC */ 573 struct delayed_work work; 574 575 /* 576 * Used to report an error - by being at the global struct 577 * makes the memory allocated by the EDAC core 578 */ 579 struct edac_raw_error_desc error_desc; 580 581 /* the internal state of this controller instance */ 582 int op_state; 583 584 struct dentry *debugfs; 585 u8 fake_inject_layer[EDAC_MAX_LAYERS]; 586 bool fake_inject_ue; 587 u16 fake_inject_count; 588 }; 589 590 #define mci_for_each_dimm(mci, dimm) \ 591 for ((dimm) = (mci)->dimms[0]; \ 592 (dimm); \ 593 (dimm) = (dimm)->idx + 1 < (mci)->tot_dimms \ 594 ? (mci)->dimms[(dimm)->idx + 1] \ 595 : NULL) 596 597 /** 598 * edac_get_dimm_by_index - Get DIMM info at @index from a memory 599 * controller 600 * 601 * @mci: MC descriptor struct mem_ctl_info 602 * @index: index in the memory controller's DIMM array 603 * 604 * Returns a struct dimm_info * or NULL on failure. 605 */ 606 static inline struct dimm_info * 607 edac_get_dimm_by_index(struct mem_ctl_info *mci, int index) 608 { 609 if (index < 0 || index >= mci->tot_dimms) 610 return NULL; 611 612 if (WARN_ON_ONCE(mci->dimms[index]->idx != index)) 613 return NULL; 614 615 return mci->dimms[index]; 616 } 617 618 /** 619 * edac_get_dimm - Get DIMM info from a memory controller given by 620 * [layer0,layer1,layer2] position 621 * 622 * @mci: MC descriptor struct mem_ctl_info 623 * @layer0: layer0 position 624 * @layer1: layer1 position. Unused if n_layers < 2 625 * @layer2: layer2 position. Unused if n_layers < 3 626 * 627 * For 1 layer, this function returns "dimms[layer0]"; 628 * 629 * For 2 layers, this function is similar to allocating a two-dimensional 630 * array and returning "dimms[layer0][layer1]"; 631 * 632 * For 3 layers, this function is similar to allocating a tri-dimensional 633 * array and returning "dimms[layer0][layer1][layer2]"; 634 */ 635 static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci, 636 int layer0, int layer1, int layer2) 637 { 638 int index; 639 640 if (layer0 < 0 641 || (mci->n_layers > 1 && layer1 < 0) 642 || (mci->n_layers > 2 && layer2 < 0)) 643 return NULL; 644 645 index = layer0; 646 647 if (mci->n_layers > 1) 648 index = index * mci->layers[1].size + layer1; 649 650 if (mci->n_layers > 2) 651 index = index * mci->layers[2].size + layer2; 652 653 return edac_get_dimm_by_index(mci, index); 654 } 655 #endif /* _LINUX_EDAC_H_ */ 656