1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. 4 */ 5 #ifndef LINUX_DMAENGINE_H 6 #define LINUX_DMAENGINE_H 7 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/uio.h> 11 #include <linux/bug.h> 12 #include <linux/scatterlist.h> 13 #include <linux/bitmap.h> 14 #include <linux/types.h> 15 #include <asm/page.h> 16 17 /** 18 * typedef dma_cookie_t - an opaque DMA cookie 19 * 20 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code 21 */ 22 typedef s32 dma_cookie_t; 23 #define DMA_MIN_COOKIE 1 24 25 static inline int dma_submit_error(dma_cookie_t cookie) 26 { 27 return cookie < 0 ? cookie : 0; 28 } 29 30 /** 31 * enum dma_status - DMA transaction status 32 * @DMA_COMPLETE: transaction completed 33 * @DMA_IN_PROGRESS: transaction not yet processed 34 * @DMA_PAUSED: transaction is paused 35 * @DMA_ERROR: transaction failed 36 */ 37 enum dma_status { 38 DMA_COMPLETE, 39 DMA_IN_PROGRESS, 40 DMA_PAUSED, 41 DMA_ERROR, 42 DMA_OUT_OF_ORDER, 43 }; 44 45 /** 46 * enum dma_transaction_type - DMA transaction types/indexes 47 * 48 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is 49 * automatically set as dma devices are registered. 50 */ 51 enum dma_transaction_type { 52 DMA_MEMCPY, 53 DMA_XOR, 54 DMA_PQ, 55 DMA_XOR_VAL, 56 DMA_PQ_VAL, 57 DMA_MEMSET, 58 DMA_MEMSET_SG, 59 DMA_INTERRUPT, 60 DMA_PRIVATE, 61 DMA_ASYNC_TX, 62 DMA_SLAVE, 63 DMA_CYCLIC, 64 DMA_INTERLEAVE, 65 DMA_COMPLETION_NO_ORDER, 66 DMA_REPEAT, 67 DMA_LOAD_EOT, 68 /* last transaction type for creation of the capabilities mask */ 69 DMA_TX_TYPE_END, 70 }; 71 72 /** 73 * enum dma_transfer_direction - dma transfer mode and direction indicator 74 * @DMA_MEM_TO_MEM: Async/Memcpy mode 75 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device 76 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory 77 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device 78 */ 79 enum dma_transfer_direction { 80 DMA_MEM_TO_MEM, 81 DMA_MEM_TO_DEV, 82 DMA_DEV_TO_MEM, 83 DMA_DEV_TO_DEV, 84 DMA_TRANS_NONE, 85 }; 86 87 /** 88 * Interleaved Transfer Request 89 * ---------------------------- 90 * A chunk is collection of contiguous bytes to be transferred. 91 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). 92 * ICGs may or may not change between chunks. 93 * A FRAME is the smallest series of contiguous {chunk,icg} pairs, 94 * that when repeated an integral number of times, specifies the transfer. 95 * A transfer template is specification of a Frame, the number of times 96 * it is to be repeated and other per-transfer attributes. 97 * 98 * Practically, a client driver would have ready a template for each 99 * type of transfer it is going to need during its lifetime and 100 * set only 'src_start' and 'dst_start' before submitting the requests. 101 * 102 * 103 * | Frame-1 | Frame-2 | ~ | Frame-'numf' | 104 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| 105 * 106 * == Chunk size 107 * ... ICG 108 */ 109 110 /** 111 * struct data_chunk - Element of scatter-gather list that makes a frame. 112 * @size: Number of bytes to read from source. 113 * size_dst := fn(op, size_src), so doesn't mean much for destination. 114 * @icg: Number of bytes to jump after last src/dst address of this 115 * chunk and before first src/dst address for next chunk. 116 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. 117 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. 118 * @dst_icg: Number of bytes to jump after last dst address of this 119 * chunk and before the first dst address for next chunk. 120 * Ignored if dst_inc is true and dst_sgl is false. 121 * @src_icg: Number of bytes to jump after last src address of this 122 * chunk and before the first src address for next chunk. 123 * Ignored if src_inc is true and src_sgl is false. 124 */ 125 struct data_chunk { 126 size_t size; 127 size_t icg; 128 size_t dst_icg; 129 size_t src_icg; 130 }; 131 132 /** 133 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern 134 * and attributes. 135 * @src_start: Bus address of source for the first chunk. 136 * @dst_start: Bus address of destination for the first chunk. 137 * @dir: Specifies the type of Source and Destination. 138 * @src_inc: If the source address increments after reading from it. 139 * @dst_inc: If the destination address increments after writing to it. 140 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). 141 * Otherwise, source is read contiguously (icg ignored). 142 * Ignored if src_inc is false. 143 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). 144 * Otherwise, destination is filled contiguously (icg ignored). 145 * Ignored if dst_inc is false. 146 * @numf: Number of frames in this template. 147 * @frame_size: Number of chunks in a frame i.e, size of sgl[]. 148 * @sgl: Array of {chunk,icg} pairs that make up a frame. 149 */ 150 struct dma_interleaved_template { 151 dma_addr_t src_start; 152 dma_addr_t dst_start; 153 enum dma_transfer_direction dir; 154 bool src_inc; 155 bool dst_inc; 156 bool src_sgl; 157 bool dst_sgl; 158 size_t numf; 159 size_t frame_size; 160 struct data_chunk sgl[]; 161 }; 162 163 /** 164 * enum dma_ctrl_flags - DMA flags to augment operation preparation, 165 * control completion, and communicate status. 166 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of 167 * this transaction 168 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client 169 * acknowledges receipt, i.e. has a chance to establish any dependency 170 * chains 171 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q 172 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P 173 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as 174 * sources that were the result of a previous operation, in the case of a PQ 175 * operation it continues the calculation with new sources 176 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend 177 * on the result of this operation 178 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till 179 * cleared or freed 180 * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command 181 * data and the descriptor should be in different format from normal 182 * data descriptors. 183 * @DMA_PREP_REPEAT: tell the driver that the transaction shall be automatically 184 * repeated when it ends until a transaction is issued on the same channel 185 * with the DMA_PREP_LOAD_EOT flag set. This flag is only applicable to 186 * interleaved transactions and is ignored for all other transaction types. 187 * @DMA_PREP_LOAD_EOT: tell the driver that the transaction shall replace any 188 * active repeated (as indicated by DMA_PREP_REPEAT) transaction when the 189 * repeated transaction ends. Not setting this flag when the previously queued 190 * transaction is marked with DMA_PREP_REPEAT will cause the new transaction 191 * to never be processed and stay in the issued queue forever. The flag is 192 * ignored if the previous transaction is not a repeated transaction. 193 */ 194 enum dma_ctrl_flags { 195 DMA_PREP_INTERRUPT = (1 << 0), 196 DMA_CTRL_ACK = (1 << 1), 197 DMA_PREP_PQ_DISABLE_P = (1 << 2), 198 DMA_PREP_PQ_DISABLE_Q = (1 << 3), 199 DMA_PREP_CONTINUE = (1 << 4), 200 DMA_PREP_FENCE = (1 << 5), 201 DMA_CTRL_REUSE = (1 << 6), 202 DMA_PREP_CMD = (1 << 7), 203 DMA_PREP_REPEAT = (1 << 8), 204 DMA_PREP_LOAD_EOT = (1 << 9), 205 }; 206 207 /** 208 * enum sum_check_bits - bit position of pq_check_flags 209 */ 210 enum sum_check_bits { 211 SUM_CHECK_P = 0, 212 SUM_CHECK_Q = 1, 213 }; 214 215 /** 216 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations 217 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise 218 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise 219 */ 220 enum sum_check_flags { 221 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), 222 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), 223 }; 224 225 226 /** 227 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. 228 * See linux/cpumask.h 229 */ 230 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; 231 232 /** 233 * struct dma_chan_percpu - the per-CPU part of struct dma_chan 234 * @memcpy_count: transaction counter 235 * @bytes_transferred: byte counter 236 */ 237 238 /** 239 * enum dma_desc_metadata_mode - per descriptor metadata mode types supported 240 * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the 241 * client driver and it is attached (via the dmaengine_desc_attach_metadata() 242 * helper) to the descriptor. 243 * 244 * Client drivers interested to use this mode can follow: 245 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM: 246 * 1. prepare the descriptor (dmaengine_prep_*) 247 * construct the metadata in the client's buffer 248 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the 249 * descriptor 250 * 3. submit the transfer 251 * - DMA_DEV_TO_MEM: 252 * 1. prepare the descriptor (dmaengine_prep_*) 253 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the 254 * descriptor 255 * 3. submit the transfer 256 * 4. when the transfer is completed, the metadata should be available in the 257 * attached buffer 258 * 259 * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA 260 * driver. The client driver can ask for the pointer, maximum size and the 261 * currently used size of the metadata and can directly update or read it. 262 * dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is 263 * provided as helper functions. 264 * 265 * Note: the metadata area for the descriptor is no longer valid after the 266 * transfer has been completed (valid up to the point when the completion 267 * callback returns if used). 268 * 269 * Client drivers interested to use this mode can follow: 270 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM: 271 * 1. prepare the descriptor (dmaengine_prep_*) 272 * 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's 273 * metadata area 274 * 3. update the metadata at the pointer 275 * 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the amount 276 * of data the client has placed into the metadata buffer 277 * 5. submit the transfer 278 * - DMA_DEV_TO_MEM: 279 * 1. prepare the descriptor (dmaengine_prep_*) 280 * 2. submit the transfer 281 * 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the 282 * pointer to the engine's metadata area 283 * 4. Read out the metadata from the pointer 284 * 285 * Note: the two mode is not compatible and clients must use one mode for a 286 * descriptor. 287 */ 288 enum dma_desc_metadata_mode { 289 DESC_METADATA_NONE = 0, 290 DESC_METADATA_CLIENT = BIT(0), 291 DESC_METADATA_ENGINE = BIT(1), 292 }; 293 294 struct dma_chan_percpu { 295 /* stats */ 296 unsigned long memcpy_count; 297 unsigned long bytes_transferred; 298 }; 299 300 /** 301 * struct dma_router - DMA router structure 302 * @dev: pointer to the DMA router device 303 * @route_free: function to be called when the route can be disconnected 304 */ 305 struct dma_router { 306 struct device *dev; 307 void (*route_free)(struct device *dev, void *route_data); 308 }; 309 310 /** 311 * struct dma_chan - devices supply DMA channels, clients use them 312 * @device: ptr to the dma device who supplies this channel, always !%NULL 313 * @slave: ptr to the device using this channel 314 * @cookie: last cookie value returned to client 315 * @completed_cookie: last completed cookie for this channel 316 * @chan_id: channel ID for sysfs 317 * @dev: class device for sysfs 318 * @name: backlink name for sysfs 319 * @dbg_client_name: slave name for debugfs in format: 320 * dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx" 321 * @device_node: used to add this to the device chan list 322 * @local: per-cpu pointer to a struct dma_chan_percpu 323 * @client_count: how many clients are using this channel 324 * @table_count: number of appearances in the mem-to-mem allocation table 325 * @router: pointer to the DMA router structure 326 * @route_data: channel specific data for the router 327 * @private: private data for certain client-channel associations 328 */ 329 struct dma_chan { 330 struct dma_device *device; 331 struct device *slave; 332 dma_cookie_t cookie; 333 dma_cookie_t completed_cookie; 334 335 /* sysfs */ 336 int chan_id; 337 struct dma_chan_dev *dev; 338 const char *name; 339 #ifdef CONFIG_DEBUG_FS 340 char *dbg_client_name; 341 #endif 342 343 struct list_head device_node; 344 struct dma_chan_percpu __percpu *local; 345 int client_count; 346 int table_count; 347 348 /* DMA router */ 349 struct dma_router *router; 350 void *route_data; 351 352 void *private; 353 }; 354 355 /** 356 * struct dma_chan_dev - relate sysfs device node to backing channel device 357 * @chan: driver channel device 358 * @device: sysfs device 359 * @dev_id: parent dma_device dev_id 360 * @chan_dma_dev: The channel is using custom/different dma-mapping 361 * compared to the parent dma_device 362 */ 363 struct dma_chan_dev { 364 struct dma_chan *chan; 365 struct device device; 366 int dev_id; 367 bool chan_dma_dev; 368 }; 369 370 /** 371 * enum dma_slave_buswidth - defines bus width of the DMA slave 372 * device, source or target buses 373 */ 374 enum dma_slave_buswidth { 375 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, 376 DMA_SLAVE_BUSWIDTH_1_BYTE = 1, 377 DMA_SLAVE_BUSWIDTH_2_BYTES = 2, 378 DMA_SLAVE_BUSWIDTH_3_BYTES = 3, 379 DMA_SLAVE_BUSWIDTH_4_BYTES = 4, 380 DMA_SLAVE_BUSWIDTH_8_BYTES = 8, 381 DMA_SLAVE_BUSWIDTH_16_BYTES = 16, 382 DMA_SLAVE_BUSWIDTH_32_BYTES = 32, 383 DMA_SLAVE_BUSWIDTH_64_BYTES = 64, 384 }; 385 386 /** 387 * struct dma_slave_config - dma slave channel runtime config 388 * @direction: whether the data shall go in or out on this slave 389 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are 390 * legal values. DEPRECATED, drivers should use the direction argument 391 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or 392 * the dir field in the dma_interleaved_template structure. 393 * @src_addr: this is the physical address where DMA slave data 394 * should be read (RX), if the source is memory this argument is 395 * ignored. 396 * @dst_addr: this is the physical address where DMA slave data 397 * should be written (TX), if the source is memory this argument 398 * is ignored. 399 * @src_addr_width: this is the width in bytes of the source (RX) 400 * register where DMA data shall be read. If the source 401 * is memory this may be ignored depending on architecture. 402 * Legal values: 1, 2, 3, 4, 8, 16, 32, 64. 403 * @dst_addr_width: same as src_addr_width but for destination 404 * target (TX) mutatis mutandis. 405 * @src_maxburst: the maximum number of words (note: words, as in 406 * units of the src_addr_width member, not bytes) that can be sent 407 * in one burst to the device. Typically something like half the 408 * FIFO depth on I/O peripherals so you don't overflow it. This 409 * may or may not be applicable on memory sources. 410 * @dst_maxburst: same as src_maxburst but for destination target 411 * mutatis mutandis. 412 * @src_port_window_size: The length of the register area in words the data need 413 * to be accessed on the device side. It is only used for devices which is using 414 * an area instead of a single register to receive the data. Typically the DMA 415 * loops in this area in order to transfer the data. 416 * @dst_port_window_size: same as src_port_window_size but for the destination 417 * port. 418 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill 419 * with 'true' if peripheral should be flow controller. Direction will be 420 * selected at Runtime. 421 * @slave_id: Slave requester id. Only valid for slave channels. The dma 422 * slave peripheral will have unique id as dma requester which need to be 423 * pass as slave config. 424 * @peripheral_config: peripheral configuration for programming peripheral 425 * for dmaengine transfer 426 * @peripheral_size: peripheral configuration buffer size 427 * 428 * This struct is passed in as configuration data to a DMA engine 429 * in order to set up a certain channel for DMA transport at runtime. 430 * The DMA device/engine has to provide support for an additional 431 * callback in the dma_device structure, device_config and this struct 432 * will then be passed in as an argument to the function. 433 * 434 * The rationale for adding configuration information to this struct is as 435 * follows: if it is likely that more than one DMA slave controllers in 436 * the world will support the configuration option, then make it generic. 437 * If not: if it is fixed so that it be sent in static from the platform 438 * data, then prefer to do that. 439 */ 440 struct dma_slave_config { 441 enum dma_transfer_direction direction; 442 phys_addr_t src_addr; 443 phys_addr_t dst_addr; 444 enum dma_slave_buswidth src_addr_width; 445 enum dma_slave_buswidth dst_addr_width; 446 u32 src_maxburst; 447 u32 dst_maxburst; 448 u32 src_port_window_size; 449 u32 dst_port_window_size; 450 bool device_fc; 451 unsigned int slave_id; 452 void *peripheral_config; 453 size_t peripheral_size; 454 }; 455 456 /** 457 * enum dma_residue_granularity - Granularity of the reported transfer residue 458 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The 459 * DMA channel is only able to tell whether a descriptor has been completed or 460 * not, which means residue reporting is not supported by this channel. The 461 * residue field of the dma_tx_state field will always be 0. 462 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully 463 * completed segment of the transfer (For cyclic transfers this is after each 464 * period). This is typically implemented by having the hardware generate an 465 * interrupt after each transferred segment and then the drivers updates the 466 * outstanding residue by the size of the segment. Another possibility is if 467 * the hardware supports scatter-gather and the segment descriptor has a field 468 * which gets set after the segment has been completed. The driver then counts 469 * the number of segments without the flag set to compute the residue. 470 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred 471 * burst. This is typically only supported if the hardware has a progress 472 * register of some sort (E.g. a register with the current read/write address 473 * or a register with the amount of bursts/beats/bytes that have been 474 * transferred or still need to be transferred). 475 */ 476 enum dma_residue_granularity { 477 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, 478 DMA_RESIDUE_GRANULARITY_SEGMENT = 1, 479 DMA_RESIDUE_GRANULARITY_BURST = 2, 480 }; 481 482 /** 483 * struct dma_slave_caps - expose capabilities of a slave channel only 484 * @src_addr_widths: bit mask of src addr widths the channel supports. 485 * Width is specified in bytes, e.g. for a channel supporting 486 * a width of 4 the mask should have BIT(4) set. 487 * @dst_addr_widths: bit mask of dst addr widths the channel supports 488 * @directions: bit mask of slave directions the channel supports. 489 * Since the enum dma_transfer_direction is not defined as bit flag for 490 * each type, the dma controller should set BIT(<TYPE>) and same 491 * should be checked by controller as well 492 * @min_burst: min burst capability per-transfer 493 * @max_burst: max burst capability per-transfer 494 * @max_sg_burst: max number of SG list entries executed in a single burst 495 * DMA tansaction with no software intervention for reinitialization. 496 * Zero value means unlimited number of entries. 497 * @cmd_pause: true, if pause is supported (i.e. for reading residue or 498 * for resume later) 499 * @cmd_resume: true, if resume is supported 500 * @cmd_terminate: true, if terminate cmd is supported 501 * @residue_granularity: granularity of the reported transfer residue 502 * @descriptor_reuse: if a descriptor can be reused by client and 503 * resubmitted multiple times 504 */ 505 struct dma_slave_caps { 506 u32 src_addr_widths; 507 u32 dst_addr_widths; 508 u32 directions; 509 u32 min_burst; 510 u32 max_burst; 511 u32 max_sg_burst; 512 bool cmd_pause; 513 bool cmd_resume; 514 bool cmd_terminate; 515 enum dma_residue_granularity residue_granularity; 516 bool descriptor_reuse; 517 }; 518 519 static inline const char *dma_chan_name(struct dma_chan *chan) 520 { 521 return dev_name(&chan->dev->device); 522 } 523 524 void dma_chan_cleanup(struct kref *kref); 525 526 /** 527 * typedef dma_filter_fn - callback filter for dma_request_channel 528 * @chan: channel to be reviewed 529 * @filter_param: opaque parameter passed through dma_request_channel 530 * 531 * When this optional parameter is specified in a call to dma_request_channel a 532 * suitable channel is passed to this routine for further dispositioning before 533 * being returned. Where 'suitable' indicates a non-busy channel that 534 * satisfies the given capability mask. It returns 'true' to indicate that the 535 * channel is suitable. 536 */ 537 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); 538 539 typedef void (*dma_async_tx_callback)(void *dma_async_param); 540 541 enum dmaengine_tx_result { 542 DMA_TRANS_NOERROR = 0, /* SUCCESS */ 543 DMA_TRANS_READ_FAILED, /* Source DMA read failed */ 544 DMA_TRANS_WRITE_FAILED, /* Destination DMA write failed */ 545 DMA_TRANS_ABORTED, /* Op never submitted / aborted */ 546 }; 547 548 struct dmaengine_result { 549 enum dmaengine_tx_result result; 550 u32 residue; 551 }; 552 553 typedef void (*dma_async_tx_callback_result)(void *dma_async_param, 554 const struct dmaengine_result *result); 555 556 struct dmaengine_unmap_data { 557 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID) 558 u16 map_cnt; 559 #else 560 u8 map_cnt; 561 #endif 562 u8 to_cnt; 563 u8 from_cnt; 564 u8 bidi_cnt; 565 struct device *dev; 566 struct kref kref; 567 size_t len; 568 dma_addr_t addr[]; 569 }; 570 571 struct dma_async_tx_descriptor; 572 573 struct dma_descriptor_metadata_ops { 574 int (*attach)(struct dma_async_tx_descriptor *desc, void *data, 575 size_t len); 576 577 void *(*get_ptr)(struct dma_async_tx_descriptor *desc, 578 size_t *payload_len, size_t *max_len); 579 int (*set_len)(struct dma_async_tx_descriptor *desc, 580 size_t payload_len); 581 }; 582 583 /** 584 * struct dma_async_tx_descriptor - async transaction descriptor 585 * ---dma generic offload fields--- 586 * @cookie: tracking cookie for this transaction, set to -EBUSY if 587 * this tx is sitting on a dependency list 588 * @flags: flags to augment operation preparation, control completion, and 589 * communicate status 590 * @phys: physical address of the descriptor 591 * @chan: target channel for this operation 592 * @tx_submit: accept the descriptor, assign ordered cookie and mark the 593 * descriptor pending. To be pushed on .issue_pending() call 594 * @callback: routine to call after this operation is complete 595 * @callback_param: general parameter to pass to the callback routine 596 * @desc_metadata_mode: core managed metadata mode to protect mixed use of 597 * DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise 598 * DESC_METADATA_NONE 599 * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the 600 * DMA driver if metadata mode is supported with the descriptor 601 * ---async_tx api specific fields--- 602 * @next: at completion submit this descriptor 603 * @parent: pointer to the next level up in the dependency chain 604 * @lock: protect the parent and next pointers 605 */ 606 struct dma_async_tx_descriptor { 607 dma_cookie_t cookie; 608 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ 609 dma_addr_t phys; 610 struct dma_chan *chan; 611 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); 612 int (*desc_free)(struct dma_async_tx_descriptor *tx); 613 dma_async_tx_callback callback; 614 dma_async_tx_callback_result callback_result; 615 void *callback_param; 616 struct dmaengine_unmap_data *unmap; 617 enum dma_desc_metadata_mode desc_metadata_mode; 618 struct dma_descriptor_metadata_ops *metadata_ops; 619 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 620 struct dma_async_tx_descriptor *next; 621 struct dma_async_tx_descriptor *parent; 622 spinlock_t lock; 623 #endif 624 }; 625 626 #ifdef CONFIG_DMA_ENGINE 627 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, 628 struct dmaengine_unmap_data *unmap) 629 { 630 kref_get(&unmap->kref); 631 tx->unmap = unmap; 632 } 633 634 struct dmaengine_unmap_data * 635 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); 636 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); 637 #else 638 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, 639 struct dmaengine_unmap_data *unmap) 640 { 641 } 642 static inline struct dmaengine_unmap_data * 643 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) 644 { 645 return NULL; 646 } 647 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) 648 { 649 } 650 #endif 651 652 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) 653 { 654 if (!tx->unmap) 655 return; 656 657 dmaengine_unmap_put(tx->unmap); 658 tx->unmap = NULL; 659 } 660 661 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 662 static inline void txd_lock(struct dma_async_tx_descriptor *txd) 663 { 664 } 665 static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 666 { 667 } 668 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 669 { 670 BUG(); 671 } 672 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 673 { 674 } 675 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 676 { 677 } 678 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 679 { 680 return NULL; 681 } 682 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 683 { 684 return NULL; 685 } 686 687 #else 688 static inline void txd_lock(struct dma_async_tx_descriptor *txd) 689 { 690 spin_lock_bh(&txd->lock); 691 } 692 static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 693 { 694 spin_unlock_bh(&txd->lock); 695 } 696 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 697 { 698 txd->next = next; 699 next->parent = txd; 700 } 701 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 702 { 703 txd->parent = NULL; 704 } 705 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 706 { 707 txd->next = NULL; 708 } 709 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 710 { 711 return txd->parent; 712 } 713 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 714 { 715 return txd->next; 716 } 717 #endif 718 719 /** 720 * struct dma_tx_state - filled in to report the status of 721 * a transfer. 722 * @last: last completed DMA cookie 723 * @used: last issued DMA cookie (i.e. the one in progress) 724 * @residue: the remaining number of bytes left to transmit 725 * on the selected transfer for states DMA_IN_PROGRESS and 726 * DMA_PAUSED if this is implemented in the driver, else 0 727 * @in_flight_bytes: amount of data in bytes cached by the DMA. 728 */ 729 struct dma_tx_state { 730 dma_cookie_t last; 731 dma_cookie_t used; 732 u32 residue; 733 u32 in_flight_bytes; 734 }; 735 736 /** 737 * enum dmaengine_alignment - defines alignment of the DMA async tx 738 * buffers 739 */ 740 enum dmaengine_alignment { 741 DMAENGINE_ALIGN_1_BYTE = 0, 742 DMAENGINE_ALIGN_2_BYTES = 1, 743 DMAENGINE_ALIGN_4_BYTES = 2, 744 DMAENGINE_ALIGN_8_BYTES = 3, 745 DMAENGINE_ALIGN_16_BYTES = 4, 746 DMAENGINE_ALIGN_32_BYTES = 5, 747 DMAENGINE_ALIGN_64_BYTES = 6, 748 }; 749 750 /** 751 * struct dma_slave_map - associates slave device and it's slave channel with 752 * parameter to be used by a filter function 753 * @devname: name of the device 754 * @slave: slave channel name 755 * @param: opaque parameter to pass to struct dma_filter.fn 756 */ 757 struct dma_slave_map { 758 const char *devname; 759 const char *slave; 760 void *param; 761 }; 762 763 /** 764 * struct dma_filter - information for slave device/channel to filter_fn/param 765 * mapping 766 * @fn: filter function callback 767 * @mapcnt: number of slave device/channel in the map 768 * @map: array of channel to filter mapping data 769 */ 770 struct dma_filter { 771 dma_filter_fn fn; 772 int mapcnt; 773 const struct dma_slave_map *map; 774 }; 775 776 /** 777 * struct dma_device - info on the entity supplying DMA services 778 * @chancnt: how many DMA channels are supported 779 * @privatecnt: how many DMA channels are requested by dma_request_channel 780 * @channels: the list of struct dma_chan 781 * @global_node: list_head for global dma_device_list 782 * @filter: information for device/slave to filter function/param mapping 783 * @cap_mask: one or more dma_capability flags 784 * @desc_metadata_modes: supported metadata modes by the DMA device 785 * @max_xor: maximum number of xor sources, 0 if no capability 786 * @max_pq: maximum number of PQ sources and PQ-continue capability 787 * @copy_align: alignment shift for memcpy operations 788 * @xor_align: alignment shift for xor operations 789 * @pq_align: alignment shift for pq operations 790 * @fill_align: alignment shift for memset operations 791 * @dev_id: unique device ID 792 * @dev: struct device reference for dma mapping api 793 * @owner: owner module (automatically set based on the provided dev) 794 * @src_addr_widths: bit mask of src addr widths the device supports 795 * Width is specified in bytes, e.g. for a device supporting 796 * a width of 4 the mask should have BIT(4) set. 797 * @dst_addr_widths: bit mask of dst addr widths the device supports 798 * @directions: bit mask of slave directions the device supports. 799 * Since the enum dma_transfer_direction is not defined as bit flag for 800 * each type, the dma controller should set BIT(<TYPE>) and same 801 * should be checked by controller as well 802 * @min_burst: min burst capability per-transfer 803 * @max_burst: max burst capability per-transfer 804 * @max_sg_burst: max number of SG list entries executed in a single burst 805 * DMA tansaction with no software intervention for reinitialization. 806 * Zero value means unlimited number of entries. 807 * @residue_granularity: granularity of the transfer residue reported 808 * by tx_status 809 * @device_alloc_chan_resources: allocate resources and return the 810 * number of allocated descriptors 811 * @device_router_config: optional callback for DMA router configuration 812 * @device_free_chan_resources: release DMA channel's resources 813 * @device_prep_dma_memcpy: prepares a memcpy operation 814 * @device_prep_dma_xor: prepares a xor operation 815 * @device_prep_dma_xor_val: prepares a xor validation operation 816 * @device_prep_dma_pq: prepares a pq operation 817 * @device_prep_dma_pq_val: prepares a pqzero_sum operation 818 * @device_prep_dma_memset: prepares a memset operation 819 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list 820 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation 821 * @device_prep_slave_sg: prepares a slave dma operation 822 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. 823 * The function takes a buffer of size buf_len. The callback function will 824 * be called after period_len bytes have been transferred. 825 * @device_prep_interleaved_dma: Transfer expression in a generic way. 826 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address 827 * @device_caps: May be used to override the generic DMA slave capabilities 828 * with per-channel specific ones 829 * @device_config: Pushes a new configuration to a channel, return 0 or an error 830 * code 831 * @device_pause: Pauses any transfer happening on a channel. Returns 832 * 0 or an error code 833 * @device_resume: Resumes any transfer on a channel previously 834 * paused. Returns 0 or an error code 835 * @device_terminate_all: Aborts all transfers on a channel. Returns 0 836 * or an error code 837 * @device_synchronize: Synchronizes the termination of a transfers to the 838 * current context. 839 * @device_tx_status: poll for transaction completion, the optional 840 * txstate parameter can be supplied with a pointer to get a 841 * struct with auxiliary transfer status information, otherwise the call 842 * will just return a simple status code 843 * @device_issue_pending: push pending transactions to hardware 844 * @descriptor_reuse: a submitted transfer can be resubmitted after completion 845 * @device_release: called sometime atfer dma_async_device_unregister() is 846 * called and there are no further references to this structure. This 847 * must be implemented to free resources however many existing drivers 848 * do not and are therefore not safe to unbind while in use. 849 * @dbg_summary_show: optional routine to show contents in debugfs; default code 850 * will be used when this is omitted, but custom code can show extra, 851 * controller specific information. 852 */ 853 struct dma_device { 854 struct kref ref; 855 unsigned int chancnt; 856 unsigned int privatecnt; 857 struct list_head channels; 858 struct list_head global_node; 859 struct dma_filter filter; 860 dma_cap_mask_t cap_mask; 861 enum dma_desc_metadata_mode desc_metadata_modes; 862 unsigned short max_xor; 863 unsigned short max_pq; 864 enum dmaengine_alignment copy_align; 865 enum dmaengine_alignment xor_align; 866 enum dmaengine_alignment pq_align; 867 enum dmaengine_alignment fill_align; 868 #define DMA_HAS_PQ_CONTINUE (1 << 15) 869 870 int dev_id; 871 struct device *dev; 872 struct module *owner; 873 struct ida chan_ida; 874 struct mutex chan_mutex; /* to protect chan_ida */ 875 876 u32 src_addr_widths; 877 u32 dst_addr_widths; 878 u32 directions; 879 u32 min_burst; 880 u32 max_burst; 881 u32 max_sg_burst; 882 bool descriptor_reuse; 883 enum dma_residue_granularity residue_granularity; 884 885 int (*device_alloc_chan_resources)(struct dma_chan *chan); 886 int (*device_router_config)(struct dma_chan *chan); 887 void (*device_free_chan_resources)(struct dma_chan *chan); 888 889 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( 890 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, 891 size_t len, unsigned long flags); 892 struct dma_async_tx_descriptor *(*device_prep_dma_xor)( 893 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, 894 unsigned int src_cnt, size_t len, unsigned long flags); 895 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( 896 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, 897 size_t len, enum sum_check_flags *result, unsigned long flags); 898 struct dma_async_tx_descriptor *(*device_prep_dma_pq)( 899 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, 900 unsigned int src_cnt, const unsigned char *scf, 901 size_t len, unsigned long flags); 902 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( 903 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, 904 unsigned int src_cnt, const unsigned char *scf, size_t len, 905 enum sum_check_flags *pqres, unsigned long flags); 906 struct dma_async_tx_descriptor *(*device_prep_dma_memset)( 907 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 908 unsigned long flags); 909 struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)( 910 struct dma_chan *chan, struct scatterlist *sg, 911 unsigned int nents, int value, unsigned long flags); 912 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( 913 struct dma_chan *chan, unsigned long flags); 914 915 struct dma_async_tx_descriptor *(*device_prep_slave_sg)( 916 struct dma_chan *chan, struct scatterlist *sgl, 917 unsigned int sg_len, enum dma_transfer_direction direction, 918 unsigned long flags, void *context); 919 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( 920 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 921 size_t period_len, enum dma_transfer_direction direction, 922 unsigned long flags); 923 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( 924 struct dma_chan *chan, struct dma_interleaved_template *xt, 925 unsigned long flags); 926 struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)( 927 struct dma_chan *chan, dma_addr_t dst, u64 data, 928 unsigned long flags); 929 930 void (*device_caps)(struct dma_chan *chan, 931 struct dma_slave_caps *caps); 932 int (*device_config)(struct dma_chan *chan, 933 struct dma_slave_config *config); 934 int (*device_pause)(struct dma_chan *chan); 935 int (*device_resume)(struct dma_chan *chan); 936 int (*device_terminate_all)(struct dma_chan *chan); 937 void (*device_synchronize)(struct dma_chan *chan); 938 939 enum dma_status (*device_tx_status)(struct dma_chan *chan, 940 dma_cookie_t cookie, 941 struct dma_tx_state *txstate); 942 void (*device_issue_pending)(struct dma_chan *chan); 943 void (*device_release)(struct dma_device *dev); 944 /* debugfs support */ 945 #ifdef CONFIG_DEBUG_FS 946 void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev); 947 struct dentry *dbg_dev_root; 948 #endif 949 }; 950 951 static inline int dmaengine_slave_config(struct dma_chan *chan, 952 struct dma_slave_config *config) 953 { 954 if (chan->device->device_config) 955 return chan->device->device_config(chan, config); 956 957 return -ENOSYS; 958 } 959 960 static inline bool is_slave_direction(enum dma_transfer_direction direction) 961 { 962 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); 963 } 964 965 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( 966 struct dma_chan *chan, dma_addr_t buf, size_t len, 967 enum dma_transfer_direction dir, unsigned long flags) 968 { 969 struct scatterlist sg; 970 sg_init_table(&sg, 1); 971 sg_dma_address(&sg) = buf; 972 sg_dma_len(&sg) = len; 973 974 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 975 return NULL; 976 977 return chan->device->device_prep_slave_sg(chan, &sg, 1, 978 dir, flags, NULL); 979 } 980 981 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( 982 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 983 enum dma_transfer_direction dir, unsigned long flags) 984 { 985 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 986 return NULL; 987 988 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 989 dir, flags, NULL); 990 } 991 992 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 993 struct rio_dma_ext; 994 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( 995 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 996 enum dma_transfer_direction dir, unsigned long flags, 997 struct rio_dma_ext *rio_ext) 998 { 999 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 1000 return NULL; 1001 1002 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 1003 dir, flags, rio_ext); 1004 } 1005 #endif 1006 1007 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( 1008 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 1009 size_t period_len, enum dma_transfer_direction dir, 1010 unsigned long flags) 1011 { 1012 if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic) 1013 return NULL; 1014 1015 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, 1016 period_len, dir, flags); 1017 } 1018 1019 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( 1020 struct dma_chan *chan, struct dma_interleaved_template *xt, 1021 unsigned long flags) 1022 { 1023 if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma) 1024 return NULL; 1025 if (flags & DMA_PREP_REPEAT && 1026 !test_bit(DMA_REPEAT, chan->device->cap_mask.bits)) 1027 return NULL; 1028 1029 return chan->device->device_prep_interleaved_dma(chan, xt, flags); 1030 } 1031 1032 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset( 1033 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 1034 unsigned long flags) 1035 { 1036 if (!chan || !chan->device || !chan->device->device_prep_dma_memset) 1037 return NULL; 1038 1039 return chan->device->device_prep_dma_memset(chan, dest, value, 1040 len, flags); 1041 } 1042 1043 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy( 1044 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 1045 size_t len, unsigned long flags) 1046 { 1047 if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy) 1048 return NULL; 1049 1050 return chan->device->device_prep_dma_memcpy(chan, dest, src, 1051 len, flags); 1052 } 1053 1054 static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan, 1055 enum dma_desc_metadata_mode mode) 1056 { 1057 if (!chan) 1058 return false; 1059 1060 return !!(chan->device->desc_metadata_modes & mode); 1061 } 1062 1063 #ifdef CONFIG_DMA_ENGINE 1064 int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc, 1065 void *data, size_t len); 1066 void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc, 1067 size_t *payload_len, size_t *max_len); 1068 int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc, 1069 size_t payload_len); 1070 #else /* CONFIG_DMA_ENGINE */ 1071 static inline int dmaengine_desc_attach_metadata( 1072 struct dma_async_tx_descriptor *desc, void *data, size_t len) 1073 { 1074 return -EINVAL; 1075 } 1076 static inline void *dmaengine_desc_get_metadata_ptr( 1077 struct dma_async_tx_descriptor *desc, size_t *payload_len, 1078 size_t *max_len) 1079 { 1080 return NULL; 1081 } 1082 static inline int dmaengine_desc_set_metadata_len( 1083 struct dma_async_tx_descriptor *desc, size_t payload_len) 1084 { 1085 return -EINVAL; 1086 } 1087 #endif /* CONFIG_DMA_ENGINE */ 1088 1089 /** 1090 * dmaengine_terminate_all() - Terminate all active DMA transfers 1091 * @chan: The channel for which to terminate the transfers 1092 * 1093 * This function is DEPRECATED use either dmaengine_terminate_sync() or 1094 * dmaengine_terminate_async() instead. 1095 */ 1096 static inline int dmaengine_terminate_all(struct dma_chan *chan) 1097 { 1098 if (chan->device->device_terminate_all) 1099 return chan->device->device_terminate_all(chan); 1100 1101 return -ENOSYS; 1102 } 1103 1104 /** 1105 * dmaengine_terminate_async() - Terminate all active DMA transfers 1106 * @chan: The channel for which to terminate the transfers 1107 * 1108 * Calling this function will terminate all active and pending descriptors 1109 * that have previously been submitted to the channel. It is not guaranteed 1110 * though that the transfer for the active descriptor has stopped when the 1111 * function returns. Furthermore it is possible the complete callback of a 1112 * submitted transfer is still running when this function returns. 1113 * 1114 * dmaengine_synchronize() needs to be called before it is safe to free 1115 * any memory that is accessed by previously submitted descriptors or before 1116 * freeing any resources accessed from within the completion callback of any 1117 * previously submitted descriptors. 1118 * 1119 * This function can be called from atomic context as well as from within a 1120 * complete callback of a descriptor submitted on the same channel. 1121 * 1122 * If none of the two conditions above apply consider using 1123 * dmaengine_terminate_sync() instead. 1124 */ 1125 static inline int dmaengine_terminate_async(struct dma_chan *chan) 1126 { 1127 if (chan->device->device_terminate_all) 1128 return chan->device->device_terminate_all(chan); 1129 1130 return -EINVAL; 1131 } 1132 1133 /** 1134 * dmaengine_synchronize() - Synchronize DMA channel termination 1135 * @chan: The channel to synchronize 1136 * 1137 * Synchronizes to the DMA channel termination to the current context. When this 1138 * function returns it is guaranteed that all transfers for previously issued 1139 * descriptors have stopped and it is safe to free the memory associated 1140 * with them. Furthermore it is guaranteed that all complete callback functions 1141 * for a previously submitted descriptor have finished running and it is safe to 1142 * free resources accessed from within the complete callbacks. 1143 * 1144 * The behavior of this function is undefined if dma_async_issue_pending() has 1145 * been called between dmaengine_terminate_async() and this function. 1146 * 1147 * This function must only be called from non-atomic context and must not be 1148 * called from within a complete callback of a descriptor submitted on the same 1149 * channel. 1150 */ 1151 static inline void dmaengine_synchronize(struct dma_chan *chan) 1152 { 1153 might_sleep(); 1154 1155 if (chan->device->device_synchronize) 1156 chan->device->device_synchronize(chan); 1157 } 1158 1159 /** 1160 * dmaengine_terminate_sync() - Terminate all active DMA transfers 1161 * @chan: The channel for which to terminate the transfers 1162 * 1163 * Calling this function will terminate all active and pending transfers 1164 * that have previously been submitted to the channel. It is similar to 1165 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually 1166 * stopped and that all complete callbacks have finished running when the 1167 * function returns. 1168 * 1169 * This function must only be called from non-atomic context and must not be 1170 * called from within a complete callback of a descriptor submitted on the same 1171 * channel. 1172 */ 1173 static inline int dmaengine_terminate_sync(struct dma_chan *chan) 1174 { 1175 int ret; 1176 1177 ret = dmaengine_terminate_async(chan); 1178 if (ret) 1179 return ret; 1180 1181 dmaengine_synchronize(chan); 1182 1183 return 0; 1184 } 1185 1186 static inline int dmaengine_pause(struct dma_chan *chan) 1187 { 1188 if (chan->device->device_pause) 1189 return chan->device->device_pause(chan); 1190 1191 return -ENOSYS; 1192 } 1193 1194 static inline int dmaengine_resume(struct dma_chan *chan) 1195 { 1196 if (chan->device->device_resume) 1197 return chan->device->device_resume(chan); 1198 1199 return -ENOSYS; 1200 } 1201 1202 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, 1203 dma_cookie_t cookie, struct dma_tx_state *state) 1204 { 1205 return chan->device->device_tx_status(chan, cookie, state); 1206 } 1207 1208 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) 1209 { 1210 return desc->tx_submit(desc); 1211 } 1212 1213 static inline bool dmaengine_check_align(enum dmaengine_alignment align, 1214 size_t off1, size_t off2, size_t len) 1215 { 1216 return !(((1 << align) - 1) & (off1 | off2 | len)); 1217 } 1218 1219 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, 1220 size_t off2, size_t len) 1221 { 1222 return dmaengine_check_align(dev->copy_align, off1, off2, len); 1223 } 1224 1225 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, 1226 size_t off2, size_t len) 1227 { 1228 return dmaengine_check_align(dev->xor_align, off1, off2, len); 1229 } 1230 1231 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, 1232 size_t off2, size_t len) 1233 { 1234 return dmaengine_check_align(dev->pq_align, off1, off2, len); 1235 } 1236 1237 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, 1238 size_t off2, size_t len) 1239 { 1240 return dmaengine_check_align(dev->fill_align, off1, off2, len); 1241 } 1242 1243 static inline void 1244 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) 1245 { 1246 dma->max_pq = maxpq; 1247 if (has_pq_continue) 1248 dma->max_pq |= DMA_HAS_PQ_CONTINUE; 1249 } 1250 1251 static inline bool dmaf_continue(enum dma_ctrl_flags flags) 1252 { 1253 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; 1254 } 1255 1256 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) 1257 { 1258 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; 1259 1260 return (flags & mask) == mask; 1261 } 1262 1263 static inline bool dma_dev_has_pq_continue(struct dma_device *dma) 1264 { 1265 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; 1266 } 1267 1268 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) 1269 { 1270 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; 1271 } 1272 1273 /* dma_maxpq - reduce maxpq in the face of continued operations 1274 * @dma - dma device with PQ capability 1275 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set 1276 * 1277 * When an engine does not support native continuation we need 3 extra 1278 * source slots to reuse P and Q with the following coefficients: 1279 * 1/ {00} * P : remove P from Q', but use it as a source for P' 1280 * 2/ {01} * Q : use Q to continue Q' calculation 1281 * 3/ {00} * Q : subtract Q from P' to cancel (2) 1282 * 1283 * In the case where P is disabled we only need 1 extra source: 1284 * 1/ {01} * Q : use Q to continue Q' calculation 1285 */ 1286 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) 1287 { 1288 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) 1289 return dma_dev_to_maxpq(dma); 1290 if (dmaf_p_disabled_continue(flags)) 1291 return dma_dev_to_maxpq(dma) - 1; 1292 if (dmaf_continue(flags)) 1293 return dma_dev_to_maxpq(dma) - 3; 1294 BUG(); 1295 } 1296 1297 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg, 1298 size_t dir_icg) 1299 { 1300 if (inc) { 1301 if (dir_icg) 1302 return dir_icg; 1303 if (sgl) 1304 return icg; 1305 } 1306 1307 return 0; 1308 } 1309 1310 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt, 1311 struct data_chunk *chunk) 1312 { 1313 return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, 1314 chunk->icg, chunk->dst_icg); 1315 } 1316 1317 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt, 1318 struct data_chunk *chunk) 1319 { 1320 return dmaengine_get_icg(xt->src_inc, xt->src_sgl, 1321 chunk->icg, chunk->src_icg); 1322 } 1323 1324 /* --- public DMA engine API --- */ 1325 1326 #ifdef CONFIG_DMA_ENGINE 1327 void dmaengine_get(void); 1328 void dmaengine_put(void); 1329 #else 1330 static inline void dmaengine_get(void) 1331 { 1332 } 1333 static inline void dmaengine_put(void) 1334 { 1335 } 1336 #endif 1337 1338 #ifdef CONFIG_ASYNC_TX_DMA 1339 #define async_dmaengine_get() dmaengine_get() 1340 #define async_dmaengine_put() dmaengine_put() 1341 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 1342 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) 1343 #else 1344 #define async_dma_find_channel(type) dma_find_channel(type) 1345 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ 1346 #else 1347 static inline void async_dmaengine_get(void) 1348 { 1349 } 1350 static inline void async_dmaengine_put(void) 1351 { 1352 } 1353 static inline struct dma_chan * 1354 async_dma_find_channel(enum dma_transaction_type type) 1355 { 1356 return NULL; 1357 } 1358 #endif /* CONFIG_ASYNC_TX_DMA */ 1359 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, 1360 struct dma_chan *chan); 1361 1362 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) 1363 { 1364 tx->flags |= DMA_CTRL_ACK; 1365 } 1366 1367 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) 1368 { 1369 tx->flags &= ~DMA_CTRL_ACK; 1370 } 1371 1372 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) 1373 { 1374 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; 1375 } 1376 1377 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) 1378 static inline void 1379 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 1380 { 1381 set_bit(tx_type, dstp->bits); 1382 } 1383 1384 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) 1385 static inline void 1386 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 1387 { 1388 clear_bit(tx_type, dstp->bits); 1389 } 1390 1391 #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) 1392 static inline void __dma_cap_zero(dma_cap_mask_t *dstp) 1393 { 1394 bitmap_zero(dstp->bits, DMA_TX_TYPE_END); 1395 } 1396 1397 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) 1398 static inline int 1399 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) 1400 { 1401 return test_bit(tx_type, srcp->bits); 1402 } 1403 1404 #define for_each_dma_cap_mask(cap, mask) \ 1405 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) 1406 1407 /** 1408 * dma_async_issue_pending - flush pending transactions to HW 1409 * @chan: target DMA channel 1410 * 1411 * This allows drivers to push copies to HW in batches, 1412 * reducing MMIO writes where possible. 1413 */ 1414 static inline void dma_async_issue_pending(struct dma_chan *chan) 1415 { 1416 chan->device->device_issue_pending(chan); 1417 } 1418 1419 /** 1420 * dma_async_is_tx_complete - poll for transaction completion 1421 * @chan: DMA channel 1422 * @cookie: transaction identifier to check status of 1423 * @last: returns last completed cookie, can be NULL 1424 * @used: returns last issued cookie, can be NULL 1425 * 1426 * If @last and @used are passed in, upon return they reflect the driver 1427 * internal state and can be used with dma_async_is_complete() to check 1428 * the status of multiple cookies without re-checking hardware state. 1429 */ 1430 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, 1431 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) 1432 { 1433 struct dma_tx_state state; 1434 enum dma_status status; 1435 1436 status = chan->device->device_tx_status(chan, cookie, &state); 1437 if (last) 1438 *last = state.last; 1439 if (used) 1440 *used = state.used; 1441 return status; 1442 } 1443 1444 /** 1445 * dma_async_is_complete - test a cookie against chan state 1446 * @cookie: transaction identifier to test status of 1447 * @last_complete: last know completed transaction 1448 * @last_used: last cookie value handed out 1449 * 1450 * dma_async_is_complete() is used in dma_async_is_tx_complete() 1451 * the test logic is separated for lightweight testing of multiple cookies 1452 */ 1453 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, 1454 dma_cookie_t last_complete, dma_cookie_t last_used) 1455 { 1456 if (last_complete <= last_used) { 1457 if ((cookie <= last_complete) || (cookie > last_used)) 1458 return DMA_COMPLETE; 1459 } else { 1460 if ((cookie <= last_complete) && (cookie > last_used)) 1461 return DMA_COMPLETE; 1462 } 1463 return DMA_IN_PROGRESS; 1464 } 1465 1466 static inline void 1467 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) 1468 { 1469 if (!st) 1470 return; 1471 1472 st->last = last; 1473 st->used = used; 1474 st->residue = residue; 1475 } 1476 1477 #ifdef CONFIG_DMA_ENGINE 1478 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); 1479 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); 1480 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); 1481 void dma_issue_pending_all(void); 1482 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1483 dma_filter_fn fn, void *fn_param, 1484 struct device_node *np); 1485 1486 struct dma_chan *dma_request_chan(struct device *dev, const char *name); 1487 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask); 1488 1489 void dma_release_channel(struct dma_chan *chan); 1490 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); 1491 #else 1492 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) 1493 { 1494 return NULL; 1495 } 1496 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) 1497 { 1498 return DMA_COMPLETE; 1499 } 1500 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) 1501 { 1502 return DMA_COMPLETE; 1503 } 1504 static inline void dma_issue_pending_all(void) 1505 { 1506 } 1507 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1508 dma_filter_fn fn, 1509 void *fn_param, 1510 struct device_node *np) 1511 { 1512 return NULL; 1513 } 1514 static inline struct dma_chan *dma_request_chan(struct device *dev, 1515 const char *name) 1516 { 1517 return ERR_PTR(-ENODEV); 1518 } 1519 static inline struct dma_chan *dma_request_chan_by_mask( 1520 const dma_cap_mask_t *mask) 1521 { 1522 return ERR_PTR(-ENODEV); 1523 } 1524 static inline void dma_release_channel(struct dma_chan *chan) 1525 { 1526 } 1527 static inline int dma_get_slave_caps(struct dma_chan *chan, 1528 struct dma_slave_caps *caps) 1529 { 1530 return -ENXIO; 1531 } 1532 #endif 1533 1534 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx) 1535 { 1536 struct dma_slave_caps caps; 1537 int ret; 1538 1539 ret = dma_get_slave_caps(tx->chan, &caps); 1540 if (ret) 1541 return ret; 1542 1543 if (!caps.descriptor_reuse) 1544 return -EPERM; 1545 1546 tx->flags |= DMA_CTRL_REUSE; 1547 return 0; 1548 } 1549 1550 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx) 1551 { 1552 tx->flags &= ~DMA_CTRL_REUSE; 1553 } 1554 1555 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx) 1556 { 1557 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; 1558 } 1559 1560 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc) 1561 { 1562 /* this is supported for reusable desc, so check that */ 1563 if (!dmaengine_desc_test_reuse(desc)) 1564 return -EPERM; 1565 1566 return desc->desc_free(desc); 1567 } 1568 1569 /* --- DMA device --- */ 1570 1571 int dma_async_device_register(struct dma_device *device); 1572 int dmaenginem_async_device_register(struct dma_device *device); 1573 void dma_async_device_unregister(struct dma_device *device); 1574 int dma_async_device_channel_register(struct dma_device *device, 1575 struct dma_chan *chan); 1576 void dma_async_device_channel_unregister(struct dma_device *device, 1577 struct dma_chan *chan); 1578 void dma_run_dependencies(struct dma_async_tx_descriptor *tx); 1579 #define dma_request_channel(mask, x, y) \ 1580 __dma_request_channel(&(mask), x, y, NULL) 1581 1582 /* Deprecated, please use dma_request_chan() directly */ 1583 static inline struct dma_chan * __deprecated 1584 dma_request_slave_channel(struct device *dev, const char *name) 1585 { 1586 struct dma_chan *ch = dma_request_chan(dev, name); 1587 1588 return IS_ERR(ch) ? NULL : ch; 1589 } 1590 1591 static inline struct dma_chan 1592 *dma_request_slave_channel_compat(const dma_cap_mask_t mask, 1593 dma_filter_fn fn, void *fn_param, 1594 struct device *dev, const char *name) 1595 { 1596 struct dma_chan *chan; 1597 1598 chan = dma_request_slave_channel(dev, name); 1599 if (chan) 1600 return chan; 1601 1602 if (!fn || !fn_param) 1603 return NULL; 1604 1605 return __dma_request_channel(&mask, fn, fn_param, NULL); 1606 } 1607 1608 static inline char * 1609 dmaengine_get_direction_text(enum dma_transfer_direction dir) 1610 { 1611 switch (dir) { 1612 case DMA_DEV_TO_MEM: 1613 return "DEV_TO_MEM"; 1614 case DMA_MEM_TO_DEV: 1615 return "MEM_TO_DEV"; 1616 case DMA_MEM_TO_MEM: 1617 return "MEM_TO_MEM"; 1618 case DMA_DEV_TO_DEV: 1619 return "DEV_TO_DEV"; 1620 default: 1621 return "invalid"; 1622 } 1623 } 1624 1625 static inline struct device *dmaengine_get_dma_device(struct dma_chan *chan) 1626 { 1627 if (chan->dev->chan_dma_dev) 1628 return &chan->dev->device; 1629 1630 return chan->device->dev; 1631 } 1632 1633 #endif /* DMAENGINE_H */ 1634