1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * TI clock drivers support 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 */ 7 #ifndef __LINUX_CLK_TI_H__ 8 #define __LINUX_CLK_TI_H__ 9 10 #include <linux/clk-provider.h> 11 #include <linux/clkdev.h> 12 13 /** 14 * struct clk_omap_reg - OMAP register declaration 15 * @offset: offset from the master IP module base address 16 * @index: index of the master IP module 17 */ 18 struct clk_omap_reg { 19 void __iomem *ptr; 20 u16 offset; 21 u8 index; 22 u8 flags; 23 }; 24 25 /** 26 * struct dpll_data - DPLL registers and integration data 27 * @mult_div1_reg: register containing the DPLL M and N bitfields 28 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg 29 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg 30 * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input 31 * @clk_ref: struct clk_hw pointer to the clock's reference clock input 32 * @control_reg: register containing the DPLL mode bitfield 33 * @enable_mask: mask of the DPLL mode bitfield in @control_reg 34 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() 35 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() 36 * @last_rounded_m4xen: cache of the last M4X result of 37 * omap4_dpll_regm4xen_round_rate() 38 * @last_rounded_lpmode: cache of the last lpmode result of 39 * omap4_dpll_lpmode_recalc() 40 * @max_multiplier: maximum valid non-bypass multiplier value (actual) 41 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() 42 * @min_divider: minimum valid non-bypass divider value (actual) 43 * @max_divider: maximum valid non-bypass divider value (actual) 44 * @max_rate: maximum clock rate for the DPLL 45 * @modes: possible values of @enable_mask 46 * @autoidle_reg: register containing the DPLL autoidle mode bitfield 47 * @idlest_reg: register containing the DPLL idle status bitfield 48 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg 49 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg 50 * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg 51 * @dcc_rate: rate atleast which DCC @dcc_mask must be set 52 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg 53 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg 54 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg 55 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg 56 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs 57 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs 58 * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading 59 * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency 60 * @ssc_modfreq_mant_mask: mask of the mantissa component in @ssc_modfreq_reg 61 * @ssc_modfreq_exp_mask: mask of the exponent component in @ssc_modfreq_reg 62 * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg 63 * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in 64 * @control_reg 65 * @ssc_modfreq: the DPLL SSC frequency modulation in kHz 66 * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent) 67 * @ssc_downspread: require the only low frequency spread of the DPLL in SSC 68 * mode 69 * @flags: DPLL type/features (see below) 70 * 71 * Possible values for @flags: 72 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) 73 * 74 * @freqsel_mask is only used on the OMAP34xx family and AM35xx. 75 * 76 * XXX Some DPLLs have multiple bypass inputs, so it's not technically 77 * correct to only have one @clk_bypass pointer. 78 * 79 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, 80 * @last_rounded_n) should be separated from the runtime-fixed fields 81 * and placed into a different structure, so that the runtime-fixed data 82 * can be placed into read-only space. 83 */ 84 struct dpll_data { 85 struct clk_omap_reg mult_div1_reg; 86 u32 mult_mask; 87 u32 div1_mask; 88 struct clk_hw *clk_bypass; 89 struct clk_hw *clk_ref; 90 struct clk_omap_reg control_reg; 91 u32 enable_mask; 92 unsigned long last_rounded_rate; 93 u16 last_rounded_m; 94 u8 last_rounded_m4xen; 95 u8 last_rounded_lpmode; 96 u16 max_multiplier; 97 u8 last_rounded_n; 98 u8 min_divider; 99 u16 max_divider; 100 unsigned long max_rate; 101 u8 modes; 102 struct clk_omap_reg autoidle_reg; 103 struct clk_omap_reg idlest_reg; 104 u32 autoidle_mask; 105 u32 freqsel_mask; 106 u32 idlest_mask; 107 u32 dco_mask; 108 u32 sddiv_mask; 109 u32 dcc_mask; 110 unsigned long dcc_rate; 111 u32 lpmode_mask; 112 u32 m4xen_mask; 113 u8 auto_recal_bit; 114 u8 recal_en_bit; 115 u8 recal_st_bit; 116 struct clk_omap_reg ssc_deltam_reg; 117 struct clk_omap_reg ssc_modfreq_reg; 118 u32 ssc_deltam_int_mask; 119 u32 ssc_deltam_frac_mask; 120 u32 ssc_modfreq_mant_mask; 121 u32 ssc_modfreq_exp_mask; 122 u32 ssc_enable_mask; 123 u32 ssc_downspread_mask; 124 u32 ssc_modfreq; 125 u32 ssc_deltam; 126 bool ssc_downspread; 127 u8 flags; 128 }; 129 130 struct clk_hw_omap; 131 132 /** 133 * struct clk_hw_omap_ops - OMAP clk ops 134 * @find_idlest: find idlest register information for a clock 135 * @find_companion: find companion clock register information for a clock, 136 * basically converts CM_ICLKEN* <-> CM_FCLKEN* 137 * @allow_idle: enables autoidle hardware functionality for a clock 138 * @deny_idle: prevent autoidle hardware functionality for a clock 139 */ 140 struct clk_hw_omap_ops { 141 void (*find_idlest)(struct clk_hw_omap *oclk, 142 struct clk_omap_reg *idlest_reg, 143 u8 *idlest_bit, u8 *idlest_val); 144 void (*find_companion)(struct clk_hw_omap *oclk, 145 struct clk_omap_reg *other_reg, 146 u8 *other_bit); 147 void (*allow_idle)(struct clk_hw_omap *oclk); 148 void (*deny_idle)(struct clk_hw_omap *oclk); 149 }; 150 151 /** 152 * struct clk_hw_omap - OMAP struct clk 153 * @node: list_head connecting this clock into the full clock list 154 * @enable_reg: register to write to enable the clock (see @enable_bit) 155 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) 156 * @flags: see "struct clk.flags possibilities" above 157 * @clksel_reg: for clksel clks, register va containing src/divisor select 158 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock 159 * @clkdm_name: clockdomain name that this clock is contained in 160 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime 161 * @ops: clock ops for this clock 162 */ 163 struct clk_hw_omap { 164 struct clk_hw hw; 165 struct list_head node; 166 unsigned long fixed_rate; 167 u8 fixed_div; 168 struct clk_omap_reg enable_reg; 169 u8 enable_bit; 170 unsigned long flags; 171 struct clk_omap_reg clksel_reg; 172 struct dpll_data *dpll_data; 173 const char *clkdm_name; 174 struct clockdomain *clkdm; 175 const struct clk_hw_omap_ops *ops; 176 u32 context; 177 int autoidle_count; 178 }; 179 180 /* 181 * struct clk_hw_omap.flags possibilities 182 * 183 * XXX document the rest of the clock flags here 184 * 185 * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed 186 * with 32bit ops, by default OMAP1 uses 16bit ops. 187 * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support. 188 * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent 189 * clock is put to no-idle mode. 190 * ENABLE_ON_INIT: Clock is enabled on init. 191 * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0' 192 * disable. This inverts the behavior making '0' enable and '1' disable. 193 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL 194 * bits share the same register. This flag allows the 195 * omap4_dpllmx*() code to determine which GATE_CTRL bit field 196 * should be used. This is a temporary solution - a better approach 197 * would be to associate clock type-specific data with the clock, 198 * similar to the struct dpll_data approach. 199 */ 200 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ 201 #define CLOCK_IDLE_CONTROL (1 << 1) 202 #define CLOCK_NO_IDLE_PARENT (1 << 2) 203 #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ 204 #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 205 #define CLOCK_CLKOUTX2 (1 << 5) 206 207 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ 208 #define DPLL_LOW_POWER_STOP 0x1 209 #define DPLL_LOW_POWER_BYPASS 0x5 210 #define DPLL_LOCKED 0x7 211 212 /* DPLL Type and DCO Selection Flags */ 213 #define DPLL_J_TYPE 0x1 214 215 /* Static memmap indices */ 216 enum { 217 TI_CLKM_CM = 0, 218 TI_CLKM_CM2, 219 TI_CLKM_PRM, 220 TI_CLKM_SCRM, 221 TI_CLKM_CTRL, 222 TI_CLKM_CTRL_AUX, 223 TI_CLKM_PLLSS, 224 CLK_MAX_MEMMAPS 225 }; 226 227 /** 228 * struct ti_clk_ll_ops - low-level ops for clocks 229 * @clk_readl: pointer to register read function 230 * @clk_writel: pointer to register write function 231 * @clk_rmw: pointer to register read-modify-write function 232 * @clkdm_clk_enable: pointer to clockdomain enable function 233 * @clkdm_clk_disable: pointer to clockdomain disable function 234 * @clkdm_lookup: pointer to clockdomain lookup function 235 * @cm_wait_module_ready: pointer to CM module wait ready function 236 * @cm_split_idlest_reg: pointer to CM module function to split idlest reg 237 * 238 * Low-level ops are generally used by the basic clock types (clk-gate, 239 * clk-mux, clk-divider etc.) to provide support for various low-level 240 * hadrware interfaces (direct MMIO, regmap etc.), and is initialized 241 * by board code. Low-level ops also contain some other platform specific 242 * operations not provided directly by clock drivers. 243 */ 244 struct ti_clk_ll_ops { 245 u32 (*clk_readl)(const struct clk_omap_reg *reg); 246 void (*clk_writel)(u32 val, const struct clk_omap_reg *reg); 247 void (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg); 248 int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk); 249 int (*clkdm_clk_disable)(struct clockdomain *clkdm, 250 struct clk *clk); 251 struct clockdomain * (*clkdm_lookup)(const char *name); 252 int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg, 253 u8 idlest_shift); 254 int (*cm_split_idlest_reg)(struct clk_omap_reg *idlest_reg, 255 s16 *prcm_inst, u8 *idlest_reg_id); 256 }; 257 258 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) 259 260 bool omap2_clk_is_hw_omap(struct clk_hw *hw); 261 int omap2_clk_disable_autoidle_all(void); 262 int omap2_clk_enable_autoidle_all(void); 263 int omap2_clk_allow_idle(struct clk *clk); 264 int omap2_clk_deny_idle(struct clk *clk); 265 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, 266 unsigned long parent_rate); 267 int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, 268 unsigned long parent_rate); 269 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); 270 void omap2xxx_clkt_vps_init(void); 271 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); 272 273 void ti_dt_clk_init_retry_clks(void); 274 void ti_dt_clockdomains_setup(void); 275 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops); 276 277 struct regmap; 278 279 int omap2_clk_provider_init(struct device_node *parent, int index, 280 struct regmap *syscon, void __iomem *mem); 281 void omap2_clk_legacy_provider_init(int index, void __iomem *mem); 282 283 int omap3430_dt_clk_init(void); 284 int omap3630_dt_clk_init(void); 285 int am35xx_dt_clk_init(void); 286 int dm814x_dt_clk_init(void); 287 int dm816x_dt_clk_init(void); 288 int omap4xxx_dt_clk_init(void); 289 int omap5xxx_dt_clk_init(void); 290 int dra7xx_dt_clk_init(void); 291 int am33xx_dt_clk_init(void); 292 int am43xx_dt_clk_init(void); 293 int omap2420_dt_clk_init(void); 294 int omap2430_dt_clk_init(void); 295 296 struct ti_clk_features { 297 u32 flags; 298 long fint_min; 299 long fint_max; 300 long fint_band1_max; 301 long fint_band2_min; 302 u8 dpll_bypass_vals; 303 u8 cm_idlest_val; 304 }; 305 306 #define TI_CLK_DPLL_HAS_FREQSEL BIT(0) 307 #define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1) 308 #define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) 309 #define TI_CLK_ERRATA_I810 BIT(3) 310 #define TI_CLK_CLKCTRL_COMPAT BIT(4) 311 #define TI_CLK_DEVICE_TYPE_GP BIT(5) 312 313 void ti_clk_setup_features(struct ti_clk_features *features); 314 const struct ti_clk_features *ti_clk_get_features(void); 315 bool ti_clk_is_in_standby(struct clk *clk); 316 int omap3_noncore_dpll_save_context(struct clk_hw *hw); 317 void omap3_noncore_dpll_restore_context(struct clk_hw *hw); 318 319 int omap3_core_dpll_save_context(struct clk_hw *hw); 320 void omap3_core_dpll_restore_context(struct clk_hw *hw); 321 322 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; 323 324 #ifdef CONFIG_ATAGS 325 int omap3430_clk_legacy_init(void); 326 int omap3430es1_clk_legacy_init(void); 327 int omap36xx_clk_legacy_init(void); 328 int am35xx_clk_legacy_init(void); 329 #else 330 static inline int omap3430_clk_legacy_init(void) { return -ENXIO; } 331 static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; } 332 static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; } 333 static inline int am35xx_clk_legacy_init(void) { return -ENXIO; } 334 #endif 335 336 337 #endif 338