1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 5 */ 6 #ifndef __LINUX_CLK_PROVIDER_H 7 #define __LINUX_CLK_PROVIDER_H 8 9 #include <linux/of.h> 10 #include <linux/of_clk.h> 11 12 /* 13 * flags used across common struct clk. these flags should only affect the 14 * top-level framework. custom flags for dealing with hardware specifics 15 * belong in struct clk_foo 16 * 17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here! 18 */ 19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 23 /* unused */ 24 /* unused */ 25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ 29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ 30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ 31 /* parents need enable during gate/ungate, set rate and re-parent */ 32 #define CLK_OPS_PARENT_ENABLE BIT(12) 33 /* duty cycle call may be forwarded to the parent clock */ 34 #define CLK_DUTY_CYCLE_PARENT BIT(13) 35 36 struct clk; 37 struct clk_hw; 38 struct clk_core; 39 struct dentry; 40 41 /** 42 * struct clk_rate_request - Structure encoding the clk constraints that 43 * a clock user might require. 44 * 45 * @rate: Requested clock rate. This field will be adjusted by 46 * clock drivers according to hardware capabilities. 47 * @min_rate: Minimum rate imposed by clk users. 48 * @max_rate: Maximum rate imposed by clk users. 49 * @best_parent_rate: The best parent rate a parent can provide to fulfill the 50 * requested constraints. 51 * @best_parent_hw: The most appropriate parent clock that fulfills the 52 * requested constraints. 53 * 54 */ 55 struct clk_rate_request { 56 unsigned long rate; 57 unsigned long min_rate; 58 unsigned long max_rate; 59 unsigned long best_parent_rate; 60 struct clk_hw *best_parent_hw; 61 }; 62 63 /** 64 * struct clk_duty - Struture encoding the duty cycle ratio of a clock 65 * 66 * @num: Numerator of the duty cycle ratio 67 * @den: Denominator of the duty cycle ratio 68 */ 69 struct clk_duty { 70 unsigned int num; 71 unsigned int den; 72 }; 73 74 /** 75 * struct clk_ops - Callback operations for hardware clocks; these are to 76 * be provided by the clock implementation, and will be called by drivers 77 * through the clk_* api. 78 * 79 * @prepare: Prepare the clock for enabling. This must not return until 80 * the clock is fully prepared, and it's safe to call clk_enable. 81 * This callback is intended to allow clock implementations to 82 * do any initialisation that may sleep. Called with 83 * prepare_lock held. 84 * 85 * @unprepare: Release the clock from its prepared state. This will typically 86 * undo any work done in the @prepare callback. Called with 87 * prepare_lock held. 88 * 89 * @is_prepared: Queries the hardware to determine if the clock is prepared. 90 * This function is allowed to sleep. Optional, if this op is not 91 * set then the prepare count will be used. 92 * 93 * @unprepare_unused: Unprepare the clock atomically. Only called from 94 * clk_disable_unused for prepare clocks with special needs. 95 * Called with prepare mutex held. This function may sleep. 96 * 97 * @enable: Enable the clock atomically. This must not return until the 98 * clock is generating a valid clock signal, usable by consumer 99 * devices. Called with enable_lock held. This function must not 100 * sleep. 101 * 102 * @disable: Disable the clock atomically. Called with enable_lock held. 103 * This function must not sleep. 104 * 105 * @is_enabled: Queries the hardware to determine if the clock is enabled. 106 * This function must not sleep. Optional, if this op is not 107 * set then the enable count will be used. 108 * 109 * @disable_unused: Disable the clock atomically. Only called from 110 * clk_disable_unused for gate clocks with special needs. 111 * Called with enable_lock held. This function must not 112 * sleep. 113 * 114 * @save_context: Save the context of the clock in prepration for poweroff. 115 * 116 * @restore_context: Restore the context of the clock after a restoration 117 * of power. 118 * 119 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 120 * parent rate is an input parameter. It is up to the caller to 121 * ensure that the prepare_mutex is held across this call. 122 * Returns the calculated rate. Optional, but recommended - if 123 * this op is not set then clock rate will be initialized to 0. 124 * 125 * @round_rate: Given a target rate as input, returns the closest rate actually 126 * supported by the clock. The parent rate is an input/output 127 * parameter. 128 * 129 * @determine_rate: Given a target rate as input, returns the closest rate 130 * actually supported by the clock, and optionally the parent clock 131 * that should be used to provide the clock rate. 132 * 133 * @set_parent: Change the input source of this clock; for clocks with multiple 134 * possible parents specify a new parent by passing in the index 135 * as a u8 corresponding to the parent in either the .parent_names 136 * or .parents arrays. This function in affect translates an 137 * array index into the value programmed into the hardware. 138 * Returns 0 on success, -EERROR otherwise. 139 * 140 * @get_parent: Queries the hardware to determine the parent of a clock. The 141 * return value is a u8 which specifies the index corresponding to 142 * the parent clock. This index can be applied to either the 143 * .parent_names or .parents arrays. In short, this function 144 * translates the parent value read from hardware into an array 145 * index. Currently only called when the clock is initialized by 146 * __clk_init. This callback is mandatory for clocks with 147 * multiple parents. It is optional (and unnecessary) for clocks 148 * with 0 or 1 parents. 149 * 150 * @set_rate: Change the rate of this clock. The requested rate is specified 151 * by the second argument, which should typically be the return 152 * of .round_rate call. The third argument gives the parent rate 153 * which is likely helpful for most .set_rate implementation. 154 * Returns 0 on success, -EERROR otherwise. 155 * 156 * @set_rate_and_parent: Change the rate and the parent of this clock. The 157 * requested rate is specified by the second argument, which 158 * should typically be the return of .round_rate call. The 159 * third argument gives the parent rate which is likely helpful 160 * for most .set_rate_and_parent implementation. The fourth 161 * argument gives the parent index. This callback is optional (and 162 * unnecessary) for clocks with 0 or 1 parents as well as 163 * for clocks that can tolerate switching the rate and the parent 164 * separately via calls to .set_parent and .set_rate. 165 * Returns 0 on success, -EERROR otherwise. 166 * 167 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 168 * is expressed in ppb (parts per billion). The parent accuracy is 169 * an input parameter. 170 * Returns the calculated accuracy. Optional - if this op is not 171 * set then clock accuracy will be initialized to parent accuracy 172 * or 0 (perfect clock) if clock has no parent. 173 * 174 * @get_phase: Queries the hardware to get the current phase of a clock. 175 * Returned values are 0-359 degrees on success, negative 176 * error codes on failure. 177 * 178 * @set_phase: Shift the phase this clock signal in degrees specified 179 * by the second argument. Valid values for degrees are 180 * 0-359. Return 0 on success, otherwise -EERROR. 181 * 182 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio 183 * of a clock. Returned values denominator cannot be 0 and must be 184 * superior or equal to the numerator. 185 * 186 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by 187 * the numerator (2nd argurment) and denominator (3rd argument). 188 * Argument must be a valid ratio (denominator > 0 189 * and >= numerator) Return 0 on success, otherwise -EERROR. 190 * 191 * @init: Perform platform-specific initialization magic. 192 * This is not used by any of the basic clock types. 193 * This callback exist for HW which needs to perform some 194 * initialisation magic for CCF to get an accurate view of the 195 * clock. It may also be used dynamic resource allocation is 196 * required. It shall not used to deal with clock parameters, 197 * such as rate or parents. 198 * Returns 0 on success, -EERROR otherwise. 199 * 200 * @terminate: Free any resource allocated by init. 201 * 202 * @debug_init: Set up type-specific debugfs entries for this clock. This 203 * is called once, after the debugfs directory entry for this 204 * clock has been created. The dentry pointer representing that 205 * directory is provided as an argument. Called with 206 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 207 * 208 * 209 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 210 * implementations to split any work between atomic (enable) and sleepable 211 * (prepare) contexts. If enabling a clock requires code that might sleep, 212 * this must be done in clk_prepare. Clock enable code that will never be 213 * called in a sleepable context may be implemented in clk_enable. 214 * 215 * Typically, drivers will call clk_prepare when a clock may be needed later 216 * (eg. when a device is opened), and clk_enable when the clock is actually 217 * required (eg. from an interrupt). Note that clk_prepare MUST have been 218 * called before clk_enable. 219 */ 220 struct clk_ops { 221 int (*prepare)(struct clk_hw *hw); 222 void (*unprepare)(struct clk_hw *hw); 223 int (*is_prepared)(struct clk_hw *hw); 224 void (*unprepare_unused)(struct clk_hw *hw); 225 int (*enable)(struct clk_hw *hw); 226 void (*disable)(struct clk_hw *hw); 227 int (*is_enabled)(struct clk_hw *hw); 228 void (*disable_unused)(struct clk_hw *hw); 229 int (*save_context)(struct clk_hw *hw); 230 void (*restore_context)(struct clk_hw *hw); 231 unsigned long (*recalc_rate)(struct clk_hw *hw, 232 unsigned long parent_rate); 233 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 234 unsigned long *parent_rate); 235 int (*determine_rate)(struct clk_hw *hw, 236 struct clk_rate_request *req); 237 int (*set_parent)(struct clk_hw *hw, u8 index); 238 u8 (*get_parent)(struct clk_hw *hw); 239 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 240 unsigned long parent_rate); 241 int (*set_rate_and_parent)(struct clk_hw *hw, 242 unsigned long rate, 243 unsigned long parent_rate, u8 index); 244 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 245 unsigned long parent_accuracy); 246 int (*get_phase)(struct clk_hw *hw); 247 int (*set_phase)(struct clk_hw *hw, int degrees); 248 int (*get_duty_cycle)(struct clk_hw *hw, 249 struct clk_duty *duty); 250 int (*set_duty_cycle)(struct clk_hw *hw, 251 struct clk_duty *duty); 252 int (*init)(struct clk_hw *hw); 253 void (*terminate)(struct clk_hw *hw); 254 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 255 }; 256 257 /** 258 * struct clk_parent_data - clk parent information 259 * @hw: parent clk_hw pointer (used for clk providers with internal clks) 260 * @fw_name: parent name local to provider registering clk 261 * @name: globally unique parent name (used as a fallback) 262 * @index: parent index local to provider registering clk (if @fw_name absent) 263 */ 264 struct clk_parent_data { 265 const struct clk_hw *hw; 266 const char *fw_name; 267 const char *name; 268 int index; 269 }; 270 271 /** 272 * struct clk_init_data - holds init data that's common to all clocks and is 273 * shared between the clock provider and the common clock framework. 274 * 275 * @name: clock name 276 * @ops: operations this clock supports 277 * @parent_names: array of string names for all possible parents 278 * @parent_data: array of parent data for all possible parents (when some 279 * parents are external to the clk controller) 280 * @parent_hws: array of pointers to all possible parents (when all parents 281 * are internal to the clk controller) 282 * @num_parents: number of possible parents 283 * @flags: framework-level hints and quirks 284 */ 285 struct clk_init_data { 286 const char *name; 287 const struct clk_ops *ops; 288 /* Only one of the following three should be assigned */ 289 const char * const *parent_names; 290 const struct clk_parent_data *parent_data; 291 const struct clk_hw **parent_hws; 292 u8 num_parents; 293 unsigned long flags; 294 }; 295 296 /** 297 * struct clk_hw - handle for traversing from a struct clk to its corresponding 298 * hardware-specific structure. struct clk_hw should be declared within struct 299 * clk_foo and then referenced by the struct clk instance that uses struct 300 * clk_foo's clk_ops 301 * 302 * @core: pointer to the struct clk_core instance that points back to this 303 * struct clk_hw instance 304 * 305 * @clk: pointer to the per-user struct clk instance that can be used to call 306 * into the clk API 307 * 308 * @init: pointer to struct clk_init_data that contains the init data shared 309 * with the common clock framework. This pointer will be set to NULL once 310 * a clk_register() variant is called on this clk_hw pointer. 311 */ 312 struct clk_hw { 313 struct clk_core *core; 314 struct clk *clk; 315 const struct clk_init_data *init; 316 }; 317 318 /* 319 * DOC: Basic clock implementations common to many platforms 320 * 321 * Each basic clock hardware type is comprised of a structure describing the 322 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 323 * unique flags for that hardware type, a registration function and an 324 * alternative macro for static initialization 325 */ 326 327 /** 328 * struct clk_fixed_rate - fixed-rate clock 329 * @hw: handle between common and hardware-specific interfaces 330 * @fixed_rate: constant frequency of clock 331 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion) 332 * @flags: hardware specific flags 333 * 334 * Flags: 335 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk 336 * instead of what's set in @fixed_accuracy. 337 */ 338 struct clk_fixed_rate { 339 struct clk_hw hw; 340 unsigned long fixed_rate; 341 unsigned long fixed_accuracy; 342 unsigned long flags; 343 }; 344 345 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0) 346 347 extern const struct clk_ops clk_fixed_rate_ops; 348 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, 349 struct device_node *np, const char *name, 350 const char *parent_name, const struct clk_hw *parent_hw, 351 const struct clk_parent_data *parent_data, unsigned long flags, 352 unsigned long fixed_rate, unsigned long fixed_accuracy, 353 unsigned long clk_fixed_flags); 354 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 355 const char *parent_name, unsigned long flags, 356 unsigned long fixed_rate); 357 /** 358 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock 359 * framework 360 * @dev: device that is registering this clock 361 * @name: name of this clock 362 * @parent_name: name of clock's parent 363 * @flags: framework-specific flags 364 * @fixed_rate: non-adjustable clock rate 365 */ 366 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ 367 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ 368 NULL, (flags), (fixed_rate), 0, 0) 369 /** 370 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with 371 * the clock framework 372 * @dev: device that is registering this clock 373 * @name: name of this clock 374 * @parent_hw: pointer to parent clk 375 * @flags: framework-specific flags 376 * @fixed_rate: non-adjustable clock rate 377 */ 378 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \ 379 fixed_rate) \ 380 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ 381 NULL, (flags), (fixed_rate), 0, 0) 382 /** 383 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with 384 * the clock framework 385 * @dev: device that is registering this clock 386 * @name: name of this clock 387 * @parent_data: parent clk data 388 * @flags: framework-specific flags 389 * @fixed_rate: non-adjustable clock rate 390 */ 391 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \ 392 fixed_rate) \ 393 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ 394 (parent_data), (flags), (fixed_rate), 0, \ 395 0) 396 /** 397 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with 398 * the clock framework 399 * @dev: device that is registering this clock 400 * @name: name of this clock 401 * @parent_name: name of clock's parent 402 * @flags: framework-specific flags 403 * @fixed_rate: non-adjustable clock rate 404 * @fixed_accuracy: non-adjustable clock accuracy 405 */ 406 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \ 407 flags, fixed_rate, \ 408 fixed_accuracy) \ 409 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \ 410 NULL, NULL, (flags), (fixed_rate), \ 411 (fixed_accuracy), 0) 412 /** 413 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate 414 * clock with the clock framework 415 * @dev: device that is registering this clock 416 * @name: name of this clock 417 * @parent_hw: pointer to parent clk 418 * @flags: framework-specific flags 419 * @fixed_rate: non-adjustable clock rate 420 * @fixed_accuracy: non-adjustable clock accuracy 421 */ 422 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ 423 parent_hw, flags, fixed_rate, fixed_accuracy) \ 424 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \ 425 NULL, NULL, (flags), (fixed_rate), \ 426 (fixed_accuracy), 0) 427 /** 428 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate 429 * clock with the clock framework 430 * @dev: device that is registering this clock 431 * @name: name of this clock 432 * @parent_name: name of clock's parent 433 * @flags: framework-specific flags 434 * @fixed_rate: non-adjustable clock rate 435 * @fixed_accuracy: non-adjustable clock accuracy 436 */ 437 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \ 438 parent_data, flags, fixed_rate, fixed_accuracy) \ 439 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ 440 (parent_data), NULL, (flags), \ 441 (fixed_rate), (fixed_accuracy), 0) 442 443 void clk_unregister_fixed_rate(struct clk *clk); 444 void clk_hw_unregister_fixed_rate(struct clk_hw *hw); 445 446 void of_fixed_clk_setup(struct device_node *np); 447 448 /** 449 * struct clk_gate - gating clock 450 * 451 * @hw: handle between common and hardware-specific interfaces 452 * @reg: register controlling gate 453 * @bit_idx: single bit controlling gate 454 * @flags: hardware-specific flags 455 * @lock: register lock 456 * 457 * Clock which can gate its output. Implements .enable & .disable 458 * 459 * Flags: 460 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 461 * enable the clock. Setting this flag does the opposite: setting the bit 462 * disable the clock and clearing it enables the clock 463 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 464 * of this register, and mask of gate bits are in higher 16-bit of this 465 * register. While setting the gate bits, higher 16-bit should also be 466 * updated to indicate changing gate bits. 467 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for 468 * the gate register. Setting this flag makes the register accesses big 469 * endian. 470 */ 471 struct clk_gate { 472 struct clk_hw hw; 473 void __iomem *reg; 474 u8 bit_idx; 475 u8 flags; 476 spinlock_t *lock; 477 }; 478 479 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 480 481 #define CLK_GATE_SET_TO_DISABLE BIT(0) 482 #define CLK_GATE_HIWORD_MASK BIT(1) 483 #define CLK_GATE_BIG_ENDIAN BIT(2) 484 485 extern const struct clk_ops clk_gate_ops; 486 struct clk_hw *__clk_hw_register_gate(struct device *dev, 487 struct device_node *np, const char *name, 488 const char *parent_name, const struct clk_hw *parent_hw, 489 const struct clk_parent_data *parent_data, 490 unsigned long flags, 491 void __iomem *reg, u8 bit_idx, 492 u8 clk_gate_flags, spinlock_t *lock); 493 struct clk *clk_register_gate(struct device *dev, const char *name, 494 const char *parent_name, unsigned long flags, 495 void __iomem *reg, u8 bit_idx, 496 u8 clk_gate_flags, spinlock_t *lock); 497 /** 498 * clk_hw_register_gate - register a gate clock with the clock framework 499 * @dev: device that is registering this clock 500 * @name: name of this clock 501 * @parent_name: name of this clock's parent 502 * @flags: framework-specific flags for this clock 503 * @reg: register address to control gating of this clock 504 * @bit_idx: which bit in the register controls gating of this clock 505 * @clk_gate_flags: gate-specific flags for this clock 506 * @lock: shared register lock for this clock 507 */ 508 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ 509 clk_gate_flags, lock) \ 510 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ 511 NULL, (flags), (reg), (bit_idx), \ 512 (clk_gate_flags), (lock)) 513 /** 514 * clk_hw_register_gate_parent_hw - register a gate clock with the clock 515 * framework 516 * @dev: device that is registering this clock 517 * @name: name of this clock 518 * @parent_hw: pointer to parent clk 519 * @flags: framework-specific flags for this clock 520 * @reg: register address to control gating of this clock 521 * @bit_idx: which bit in the register controls gating of this clock 522 * @clk_gate_flags: gate-specific flags for this clock 523 * @lock: shared register lock for this clock 524 */ 525 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \ 526 bit_idx, clk_gate_flags, lock) \ 527 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ 528 NULL, (flags), (reg), (bit_idx), \ 529 (clk_gate_flags), (lock)) 530 /** 531 * clk_hw_register_gate_parent_data - register a gate clock with the clock 532 * framework 533 * @dev: device that is registering this clock 534 * @name: name of this clock 535 * @parent_data: parent clk data 536 * @flags: framework-specific flags for this clock 537 * @reg: register address to control gating of this clock 538 * @bit_idx: which bit in the register controls gating of this clock 539 * @clk_gate_flags: gate-specific flags for this clock 540 * @lock: shared register lock for this clock 541 */ 542 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \ 543 bit_idx, clk_gate_flags, lock) \ 544 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ 545 (flags), (reg), (bit_idx), \ 546 (clk_gate_flags), (lock)) 547 void clk_unregister_gate(struct clk *clk); 548 void clk_hw_unregister_gate(struct clk_hw *hw); 549 int clk_gate_is_enabled(struct clk_hw *hw); 550 551 struct clk_div_table { 552 unsigned int val; 553 unsigned int div; 554 }; 555 556 /** 557 * struct clk_divider - adjustable divider clock 558 * 559 * @hw: handle between common and hardware-specific interfaces 560 * @reg: register containing the divider 561 * @shift: shift to the divider bit field 562 * @width: width of the divider bit field 563 * @table: array of value/divider pairs, last entry should have div = 0 564 * @lock: register lock 565 * 566 * Clock with an adjustable divider affecting its output frequency. Implements 567 * .recalc_rate, .set_rate and .round_rate 568 * 569 * Flags: 570 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 571 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 572 * the raw value read from the register, with the value of zero considered 573 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 574 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 575 * the hardware register 576 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 577 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 578 * Some hardware implementations gracefully handle this case and allow a 579 * zero divisor by not modifying their input clock 580 * (divide by one / bypass). 581 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 582 * of this register, and mask of divider bits are in higher 16-bit of this 583 * register. While setting the divider bits, higher 16-bit should also be 584 * updated to indicate changing divider bits. 585 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded 586 * to the closest integer instead of the up one. 587 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should 588 * not be changed by the clock framework. 589 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED 590 * except when the value read from the register is zero, the divisor is 591 * 2^width of the field. 592 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used 593 * for the divider register. Setting this flag makes the register accesses 594 * big endian. 595 */ 596 struct clk_divider { 597 struct clk_hw hw; 598 void __iomem *reg; 599 u8 shift; 600 u8 width; 601 u8 flags; 602 const struct clk_div_table *table; 603 spinlock_t *lock; 604 }; 605 606 #define clk_div_mask(width) ((1 << (width)) - 1) 607 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 608 609 #define CLK_DIVIDER_ONE_BASED BIT(0) 610 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 611 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 612 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 613 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 614 #define CLK_DIVIDER_READ_ONLY BIT(5) 615 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 616 #define CLK_DIVIDER_BIG_ENDIAN BIT(7) 617 618 extern const struct clk_ops clk_divider_ops; 619 extern const struct clk_ops clk_divider_ro_ops; 620 621 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, 622 unsigned int val, const struct clk_div_table *table, 623 unsigned long flags, unsigned long width); 624 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 625 unsigned long rate, unsigned long *prate, 626 const struct clk_div_table *table, 627 u8 width, unsigned long flags); 628 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 629 unsigned long rate, unsigned long *prate, 630 const struct clk_div_table *table, u8 width, 631 unsigned long flags, unsigned int val); 632 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, 633 const struct clk_div_table *table, u8 width, 634 unsigned long flags); 635 int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, 636 const struct clk_div_table *table, u8 width, 637 unsigned long flags, unsigned int val); 638 int divider_get_val(unsigned long rate, unsigned long parent_rate, 639 const struct clk_div_table *table, u8 width, 640 unsigned long flags); 641 642 struct clk_hw *__clk_hw_register_divider(struct device *dev, 643 struct device_node *np, const char *name, 644 const char *parent_name, const struct clk_hw *parent_hw, 645 const struct clk_parent_data *parent_data, unsigned long flags, 646 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, 647 const struct clk_div_table *table, spinlock_t *lock); 648 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, 649 struct device_node *np, const char *name, 650 const char *parent_name, const struct clk_hw *parent_hw, 651 const struct clk_parent_data *parent_data, unsigned long flags, 652 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, 653 const struct clk_div_table *table, spinlock_t *lock); 654 struct clk *clk_register_divider_table(struct device *dev, const char *name, 655 const char *parent_name, unsigned long flags, 656 void __iomem *reg, u8 shift, u8 width, 657 u8 clk_divider_flags, const struct clk_div_table *table, 658 spinlock_t *lock); 659 /** 660 * clk_register_divider - register a divider clock with the clock framework 661 * @dev: device registering this clock 662 * @name: name of this clock 663 * @parent_name: name of clock's parent 664 * @flags: framework-specific flags 665 * @reg: register address to adjust divider 666 * @shift: number of bits to shift the bitfield 667 * @width: width of the bitfield 668 * @clk_divider_flags: divider-specific flags for this clock 669 * @lock: shared register lock for this clock 670 */ 671 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ 672 clk_divider_flags, lock) \ 673 clk_register_divider_table((dev), (name), (parent_name), (flags), \ 674 (reg), (shift), (width), \ 675 (clk_divider_flags), NULL, (lock)) 676 /** 677 * clk_hw_register_divider - register a divider clock with the clock framework 678 * @dev: device registering this clock 679 * @name: name of this clock 680 * @parent_name: name of clock's parent 681 * @flags: framework-specific flags 682 * @reg: register address to adjust divider 683 * @shift: number of bits to shift the bitfield 684 * @width: width of the bitfield 685 * @clk_divider_flags: divider-specific flags for this clock 686 * @lock: shared register lock for this clock 687 */ 688 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ 689 width, clk_divider_flags, lock) \ 690 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ 691 NULL, (flags), (reg), (shift), (width), \ 692 (clk_divider_flags), NULL, (lock)) 693 /** 694 * clk_hw_register_divider_parent_hw - register a divider clock with the clock 695 * framework 696 * @dev: device registering this clock 697 * @name: name of this clock 698 * @parent_hw: pointer to parent clk 699 * @flags: framework-specific flags 700 * @reg: register address to adjust divider 701 * @shift: number of bits to shift the bitfield 702 * @width: width of the bitfield 703 * @clk_divider_flags: divider-specific flags for this clock 704 * @lock: shared register lock for this clock 705 */ 706 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \ 707 shift, width, clk_divider_flags, \ 708 lock) \ 709 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ 710 NULL, (flags), (reg), (shift), (width), \ 711 (clk_divider_flags), NULL, (lock)) 712 /** 713 * clk_hw_register_divider_parent_data - register a divider clock with the clock 714 * framework 715 * @dev: device registering this clock 716 * @name: name of this clock 717 * @parent_data: parent clk data 718 * @flags: framework-specific flags 719 * @reg: register address to adjust divider 720 * @shift: number of bits to shift the bitfield 721 * @width: width of the bitfield 722 * @clk_divider_flags: divider-specific flags for this clock 723 * @lock: shared register lock for this clock 724 */ 725 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \ 726 reg, shift, width, \ 727 clk_divider_flags, lock) \ 728 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ 729 (parent_data), (flags), (reg), (shift), \ 730 (width), (clk_divider_flags), NULL, (lock)) 731 /** 732 * clk_hw_register_divider_table - register a table based divider clock with 733 * the clock framework 734 * @dev: device registering this clock 735 * @name: name of this clock 736 * @parent_name: name of clock's parent 737 * @flags: framework-specific flags 738 * @reg: register address to adjust divider 739 * @shift: number of bits to shift the bitfield 740 * @width: width of the bitfield 741 * @clk_divider_flags: divider-specific flags for this clock 742 * @table: array of divider/value pairs ending with a div set to 0 743 * @lock: shared register lock for this clock 744 */ 745 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ 746 shift, width, clk_divider_flags, table, \ 747 lock) \ 748 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ 749 NULL, (flags), (reg), (shift), (width), \ 750 (clk_divider_flags), (table), (lock)) 751 /** 752 * clk_hw_register_divider_table_parent_hw - register a table based divider 753 * clock with the clock framework 754 * @dev: device registering this clock 755 * @name: name of this clock 756 * @parent_hw: pointer to parent clk 757 * @flags: framework-specific flags 758 * @reg: register address to adjust divider 759 * @shift: number of bits to shift the bitfield 760 * @width: width of the bitfield 761 * @clk_divider_flags: divider-specific flags for this clock 762 * @table: array of divider/value pairs ending with a div set to 0 763 * @lock: shared register lock for this clock 764 */ 765 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \ 766 reg, shift, width, \ 767 clk_divider_flags, table, \ 768 lock) \ 769 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ 770 NULL, (flags), (reg), (shift), (width), \ 771 (clk_divider_flags), (table), (lock)) 772 /** 773 * clk_hw_register_divider_table_parent_data - register a table based divider 774 * clock with the clock framework 775 * @dev: device registering this clock 776 * @name: name of this clock 777 * @parent_data: parent clk data 778 * @flags: framework-specific flags 779 * @reg: register address to adjust divider 780 * @shift: number of bits to shift the bitfield 781 * @width: width of the bitfield 782 * @clk_divider_flags: divider-specific flags for this clock 783 * @table: array of divider/value pairs ending with a div set to 0 784 * @lock: shared register lock for this clock 785 */ 786 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \ 787 flags, reg, shift, width, \ 788 clk_divider_flags, table, \ 789 lock) \ 790 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ 791 (parent_data), (flags), (reg), (shift), \ 792 (width), (clk_divider_flags), (table), \ 793 (lock)) 794 /** 795 * devm_clk_hw_register_divider - register a divider clock with the clock framework 796 * @dev: device registering this clock 797 * @name: name of this clock 798 * @parent_name: name of clock's parent 799 * @flags: framework-specific flags 800 * @reg: register address to adjust divider 801 * @shift: number of bits to shift the bitfield 802 * @width: width of the bitfield 803 * @clk_divider_flags: divider-specific flags for this clock 804 * @lock: shared register lock for this clock 805 */ 806 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ 807 width, clk_divider_flags, lock) \ 808 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ 809 NULL, (flags), (reg), (shift), (width), \ 810 (clk_divider_flags), NULL, (lock)) 811 /** 812 * devm_clk_hw_register_divider_table - register a table based divider clock 813 * with the clock framework (devres variant) 814 * @dev: device registering this clock 815 * @name: name of this clock 816 * @parent_name: name of clock's parent 817 * @flags: framework-specific flags 818 * @reg: register address to adjust divider 819 * @shift: number of bits to shift the bitfield 820 * @width: width of the bitfield 821 * @clk_divider_flags: divider-specific flags for this clock 822 * @table: array of divider/value pairs ending with a div set to 0 823 * @lock: shared register lock for this clock 824 */ 825 #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \ 826 reg, shift, width, \ 827 clk_divider_flags, table, lock) \ 828 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \ 829 NULL, NULL, (flags), (reg), (shift), \ 830 (width), (clk_divider_flags), (table), \ 831 (lock)) 832 833 void clk_unregister_divider(struct clk *clk); 834 void clk_hw_unregister_divider(struct clk_hw *hw); 835 836 /** 837 * struct clk_mux - multiplexer clock 838 * 839 * @hw: handle between common and hardware-specific interfaces 840 * @reg: register controlling multiplexer 841 * @table: array of register values corresponding to the parent index 842 * @shift: shift to multiplexer bit field 843 * @mask: mask of mutliplexer bit field 844 * @flags: hardware-specific flags 845 * @lock: register lock 846 * 847 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 848 * and .recalc_rate 849 * 850 * Flags: 851 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 852 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 853 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 854 * register, and mask of mux bits are in higher 16-bit of this register. 855 * While setting the mux bits, higher 16-bit should also be updated to 856 * indicate changing mux bits. 857 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the 858 * .get_parent clk_op. 859 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired 860 * frequency. 861 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for 862 * the mux register. Setting this flag makes the register accesses big 863 * endian. 864 */ 865 struct clk_mux { 866 struct clk_hw hw; 867 void __iomem *reg; 868 u32 *table; 869 u32 mask; 870 u8 shift; 871 u8 flags; 872 spinlock_t *lock; 873 }; 874 875 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) 876 877 #define CLK_MUX_INDEX_ONE BIT(0) 878 #define CLK_MUX_INDEX_BIT BIT(1) 879 #define CLK_MUX_HIWORD_MASK BIT(2) 880 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ 881 #define CLK_MUX_ROUND_CLOSEST BIT(4) 882 #define CLK_MUX_BIG_ENDIAN BIT(5) 883 884 extern const struct clk_ops clk_mux_ops; 885 extern const struct clk_ops clk_mux_ro_ops; 886 887 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, 888 const char *name, u8 num_parents, 889 const char * const *parent_names, 890 const struct clk_hw **parent_hws, 891 const struct clk_parent_data *parent_data, 892 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, 893 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 894 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np, 895 const char *name, u8 num_parents, 896 const char * const *parent_names, 897 const struct clk_hw **parent_hws, 898 const struct clk_parent_data *parent_data, 899 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, 900 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 901 struct clk *clk_register_mux_table(struct device *dev, const char *name, 902 const char * const *parent_names, u8 num_parents, 903 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, 904 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 905 906 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ 907 shift, width, clk_mux_flags, lock) \ 908 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \ 909 (flags), (reg), (shift), BIT((width)) - 1, \ 910 (clk_mux_flags), NULL, (lock)) 911 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \ 912 flags, reg, shift, mask, clk_mux_flags, \ 913 table, lock) \ 914 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 915 (parent_names), NULL, NULL, (flags), (reg), \ 916 (shift), (mask), (clk_mux_flags), (table), \ 917 (lock)) 918 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ 919 shift, width, clk_mux_flags, lock) \ 920 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 921 (parent_names), NULL, NULL, (flags), (reg), \ 922 (shift), BIT((width)) - 1, (clk_mux_flags), \ 923 NULL, (lock)) 924 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \ 925 reg, shift, width, clk_mux_flags, lock) \ 926 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ 927 (parent_hws), NULL, (flags), (reg), (shift), \ 928 BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) 929 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \ 930 flags, reg, shift, width, \ 931 clk_mux_flags, lock) \ 932 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ 933 (parent_data), (flags), (reg), (shift), \ 934 BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) 935 #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ 936 shift, width, clk_mux_flags, lock) \ 937 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 938 (parent_names), NULL, NULL, (flags), (reg), \ 939 (shift), BIT((width)) - 1, (clk_mux_flags), \ 940 NULL, (lock)) 941 942 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, 943 unsigned int val); 944 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); 945 946 void clk_unregister_mux(struct clk *clk); 947 void clk_hw_unregister_mux(struct clk_hw *hw); 948 949 void of_fixed_factor_clk_setup(struct device_node *node); 950 951 /** 952 * struct clk_fixed_factor - fixed multiplier and divider clock 953 * 954 * @hw: handle between common and hardware-specific interfaces 955 * @mult: multiplier 956 * @div: divider 957 * 958 * Clock with a fixed multiplier and divider. The output frequency is the 959 * parent clock rate divided by div and multiplied by mult. 960 * Implements .recalc_rate, .set_rate and .round_rate 961 */ 962 963 struct clk_fixed_factor { 964 struct clk_hw hw; 965 unsigned int mult; 966 unsigned int div; 967 }; 968 969 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) 970 971 extern const struct clk_ops clk_fixed_factor_ops; 972 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 973 const char *parent_name, unsigned long flags, 974 unsigned int mult, unsigned int div); 975 void clk_unregister_fixed_factor(struct clk *clk); 976 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, 977 const char *name, const char *parent_name, unsigned long flags, 978 unsigned int mult, unsigned int div); 979 void clk_hw_unregister_fixed_factor(struct clk_hw *hw); 980 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, 981 const char *name, const char *parent_name, unsigned long flags, 982 unsigned int mult, unsigned int div); 983 /** 984 * struct clk_fractional_divider - adjustable fractional divider clock 985 * 986 * @hw: handle between common and hardware-specific interfaces 987 * @reg: register containing the divider 988 * @mshift: shift to the numerator bit field 989 * @mwidth: width of the numerator bit field 990 * @nshift: shift to the denominator bit field 991 * @nwidth: width of the denominator bit field 992 * @lock: register lock 993 * 994 * Clock with adjustable fractional divider affecting its output frequency. 995 * 996 * Flags: 997 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator 998 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED 999 * is set then the numerator and denominator are both the value read 1000 * plus one. 1001 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are 1002 * used for the divider register. Setting this flag makes the register 1003 * accesses big endian. 1004 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might 1005 * be saturated and the caller will get quite far from the good enough 1006 * approximation. Instead the caller may require, by setting this flag, 1007 * to shift left by a few bits in case, when the asked one is quite small 1008 * to satisfy the desired range of denominator. It assumes that on the 1009 * caller's side the power-of-two capable prescaler exists. 1010 */ 1011 struct clk_fractional_divider { 1012 struct clk_hw hw; 1013 void __iomem *reg; 1014 u8 mshift; 1015 u8 mwidth; 1016 u32 mmask; 1017 u8 nshift; 1018 u8 nwidth; 1019 u32 nmask; 1020 u8 flags; 1021 void (*approximation)(struct clk_hw *hw, 1022 unsigned long rate, unsigned long *parent_rate, 1023 unsigned long *m, unsigned long *n); 1024 spinlock_t *lock; 1025 }; 1026 1027 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) 1028 1029 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) 1030 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) 1031 #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2) 1032 1033 struct clk *clk_register_fractional_divider(struct device *dev, 1034 const char *name, const char *parent_name, unsigned long flags, 1035 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 1036 u8 clk_divider_flags, spinlock_t *lock); 1037 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, 1038 const char *name, const char *parent_name, unsigned long flags, 1039 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 1040 u8 clk_divider_flags, spinlock_t *lock); 1041 void clk_hw_unregister_fractional_divider(struct clk_hw *hw); 1042 1043 /** 1044 * struct clk_multiplier - adjustable multiplier clock 1045 * 1046 * @hw: handle between common and hardware-specific interfaces 1047 * @reg: register containing the multiplier 1048 * @shift: shift to the multiplier bit field 1049 * @width: width of the multiplier bit field 1050 * @lock: register lock 1051 * 1052 * Clock with an adjustable multiplier affecting its output frequency. 1053 * Implements .recalc_rate, .set_rate and .round_rate 1054 * 1055 * Flags: 1056 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read 1057 * from the register, with 0 being a valid value effectively 1058 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is 1059 * set, then a null multiplier will be considered as a bypass, 1060 * leaving the parent rate unmodified. 1061 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be 1062 * rounded to the closest integer instead of the down one. 1063 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are 1064 * used for the multiplier register. Setting this flag makes the register 1065 * accesses big endian. 1066 */ 1067 struct clk_multiplier { 1068 struct clk_hw hw; 1069 void __iomem *reg; 1070 u8 shift; 1071 u8 width; 1072 u8 flags; 1073 spinlock_t *lock; 1074 }; 1075 1076 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) 1077 1078 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) 1079 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) 1080 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) 1081 1082 extern const struct clk_ops clk_multiplier_ops; 1083 1084 /*** 1085 * struct clk_composite - aggregate clock of mux, divider and gate clocks 1086 * 1087 * @hw: handle between common and hardware-specific interfaces 1088 * @mux_hw: handle between composite and hardware-specific mux clock 1089 * @rate_hw: handle between composite and hardware-specific rate clock 1090 * @gate_hw: handle between composite and hardware-specific gate clock 1091 * @mux_ops: clock ops for mux 1092 * @rate_ops: clock ops for rate 1093 * @gate_ops: clock ops for gate 1094 */ 1095 struct clk_composite { 1096 struct clk_hw hw; 1097 struct clk_ops ops; 1098 1099 struct clk_hw *mux_hw; 1100 struct clk_hw *rate_hw; 1101 struct clk_hw *gate_hw; 1102 1103 const struct clk_ops *mux_ops; 1104 const struct clk_ops *rate_ops; 1105 const struct clk_ops *gate_ops; 1106 }; 1107 1108 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) 1109 1110 struct clk *clk_register_composite(struct device *dev, const char *name, 1111 const char * const *parent_names, int num_parents, 1112 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1113 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1114 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1115 unsigned long flags); 1116 struct clk *clk_register_composite_pdata(struct device *dev, const char *name, 1117 const struct clk_parent_data *parent_data, int num_parents, 1118 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1119 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1120 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1121 unsigned long flags); 1122 void clk_unregister_composite(struct clk *clk); 1123 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, 1124 const char * const *parent_names, int num_parents, 1125 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1126 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1127 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1128 unsigned long flags); 1129 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev, 1130 const char *name, 1131 const struct clk_parent_data *parent_data, int num_parents, 1132 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1133 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1134 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1135 unsigned long flags); 1136 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev, 1137 const char *name, const struct clk_parent_data *parent_data, 1138 int num_parents, 1139 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1140 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1141 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1142 unsigned long flags); 1143 void clk_hw_unregister_composite(struct clk_hw *hw); 1144 1145 struct clk *clk_register(struct device *dev, struct clk_hw *hw); 1146 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 1147 1148 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); 1149 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); 1150 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw); 1151 1152 void clk_unregister(struct clk *clk); 1153 void devm_clk_unregister(struct device *dev, struct clk *clk); 1154 1155 void clk_hw_unregister(struct clk_hw *hw); 1156 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); 1157 1158 /* helper functions */ 1159 const char *__clk_get_name(const struct clk *clk); 1160 const char *clk_hw_get_name(const struct clk_hw *hw); 1161 #ifdef CONFIG_COMMON_CLK 1162 struct clk_hw *__clk_get_hw(struct clk *clk); 1163 #else 1164 static inline struct clk_hw *__clk_get_hw(struct clk *clk) 1165 { 1166 return (struct clk_hw *)clk; 1167 } 1168 #endif 1169 1170 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id); 1171 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw, 1172 const char *con_id); 1173 1174 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); 1175 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); 1176 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, 1177 unsigned int index); 1178 int clk_hw_get_parent_index(struct clk_hw *hw); 1179 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); 1180 unsigned int __clk_get_enable_count(struct clk *clk); 1181 unsigned long clk_hw_get_rate(const struct clk_hw *hw); 1182 unsigned long clk_hw_get_flags(const struct clk_hw *hw); 1183 #define clk_hw_can_set_rate_parent(hw) \ 1184 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) 1185 1186 bool clk_hw_is_prepared(const struct clk_hw *hw); 1187 bool clk_hw_rate_is_protected(const struct clk_hw *hw); 1188 bool clk_hw_is_enabled(const struct clk_hw *hw); 1189 bool __clk_is_enabled(struct clk *clk); 1190 struct clk *__clk_lookup(const char *name); 1191 int __clk_mux_determine_rate(struct clk_hw *hw, 1192 struct clk_rate_request *req); 1193 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); 1194 int __clk_mux_determine_rate_closest(struct clk_hw *hw, 1195 struct clk_rate_request *req); 1196 int clk_mux_determine_rate_flags(struct clk_hw *hw, 1197 struct clk_rate_request *req, 1198 unsigned long flags); 1199 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); 1200 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, 1201 unsigned long max_rate); 1202 1203 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) 1204 { 1205 dst->clk = src->clk; 1206 dst->core = src->core; 1207 } 1208 1209 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, 1210 unsigned long *prate, 1211 const struct clk_div_table *table, 1212 u8 width, unsigned long flags) 1213 { 1214 return divider_round_rate_parent(hw, clk_hw_get_parent(hw), 1215 rate, prate, table, width, flags); 1216 } 1217 1218 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, 1219 unsigned long *prate, 1220 const struct clk_div_table *table, 1221 u8 width, unsigned long flags, 1222 unsigned int val) 1223 { 1224 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), 1225 rate, prate, table, width, flags, 1226 val); 1227 } 1228 1229 /* 1230 * FIXME clock api without lock protection 1231 */ 1232 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); 1233 1234 struct clk_onecell_data { 1235 struct clk **clks; 1236 unsigned int clk_num; 1237 }; 1238 1239 struct clk_hw_onecell_data { 1240 unsigned int num; 1241 struct clk_hw *hws[]; 1242 }; 1243 1244 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) 1245 1246 /* 1247 * Use this macro when you have a driver that requires two initialization 1248 * routines, one at of_clk_init(), and one at platform device probe 1249 */ 1250 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ 1251 static void __init name##_of_clk_init_driver(struct device_node *np) \ 1252 { \ 1253 of_node_clear_flag(np, OF_POPULATED); \ 1254 fn(np); \ 1255 } \ 1256 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) 1257 1258 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ 1259 (&(struct clk_init_data) { \ 1260 .flags = _flags, \ 1261 .name = _name, \ 1262 .parent_names = (const char *[]) { _parent }, \ 1263 .num_parents = 1, \ 1264 .ops = _ops, \ 1265 }) 1266 1267 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ 1268 (&(struct clk_init_data) { \ 1269 .flags = _flags, \ 1270 .name = _name, \ 1271 .parent_hws = (const struct clk_hw*[]) { _parent }, \ 1272 .num_parents = 1, \ 1273 .ops = _ops, \ 1274 }) 1275 1276 /* 1277 * This macro is intended for drivers to be able to share the otherwise 1278 * individual struct clk_hw[] compound literals created by the compiler 1279 * when using CLK_HW_INIT_HW. It does NOT support multiple parents. 1280 */ 1281 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ 1282 (&(struct clk_init_data) { \ 1283 .flags = _flags, \ 1284 .name = _name, \ 1285 .parent_hws = _parent, \ 1286 .num_parents = 1, \ 1287 .ops = _ops, \ 1288 }) 1289 1290 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ 1291 (&(struct clk_init_data) { \ 1292 .flags = _flags, \ 1293 .name = _name, \ 1294 .parent_data = (const struct clk_parent_data[]) { \ 1295 { .fw_name = _parent }, \ 1296 }, \ 1297 .num_parents = 1, \ 1298 .ops = _ops, \ 1299 }) 1300 1301 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ 1302 (&(struct clk_init_data) { \ 1303 .flags = _flags, \ 1304 .name = _name, \ 1305 .parent_names = _parents, \ 1306 .num_parents = ARRAY_SIZE(_parents), \ 1307 .ops = _ops, \ 1308 }) 1309 1310 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ 1311 (&(struct clk_init_data) { \ 1312 .flags = _flags, \ 1313 .name = _name, \ 1314 .parent_hws = _parents, \ 1315 .num_parents = ARRAY_SIZE(_parents), \ 1316 .ops = _ops, \ 1317 }) 1318 1319 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ 1320 (&(struct clk_init_data) { \ 1321 .flags = _flags, \ 1322 .name = _name, \ 1323 .parent_data = _parents, \ 1324 .num_parents = ARRAY_SIZE(_parents), \ 1325 .ops = _ops, \ 1326 }) 1327 1328 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ 1329 (&(struct clk_init_data) { \ 1330 .flags = _flags, \ 1331 .name = _name, \ 1332 .parent_names = NULL, \ 1333 .num_parents = 0, \ 1334 .ops = _ops, \ 1335 }) 1336 1337 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ 1338 _div, _mult, _flags) \ 1339 struct clk_fixed_factor _struct = { \ 1340 .div = _div, \ 1341 .mult = _mult, \ 1342 .hw.init = CLK_HW_INIT(_name, \ 1343 _parent, \ 1344 &clk_fixed_factor_ops, \ 1345 _flags), \ 1346 } 1347 1348 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \ 1349 _div, _mult, _flags) \ 1350 struct clk_fixed_factor _struct = { \ 1351 .div = _div, \ 1352 .mult = _mult, \ 1353 .hw.init = CLK_HW_INIT_HW(_name, \ 1354 _parent, \ 1355 &clk_fixed_factor_ops, \ 1356 _flags), \ 1357 } 1358 1359 /* 1360 * This macro allows the driver to reuse the _parent array for multiple 1361 * fixed factor clk declarations. 1362 */ 1363 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \ 1364 _div, _mult, _flags) \ 1365 struct clk_fixed_factor _struct = { \ 1366 .div = _div, \ 1367 .mult = _mult, \ 1368 .hw.init = CLK_HW_INIT_HWS(_name, \ 1369 _parent, \ 1370 &clk_fixed_factor_ops, \ 1371 _flags), \ 1372 } 1373 1374 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \ 1375 _div, _mult, _flags) \ 1376 struct clk_fixed_factor _struct = { \ 1377 .div = _div, \ 1378 .mult = _mult, \ 1379 .hw.init = CLK_HW_INIT_FW_NAME(_name, \ 1380 _parent, \ 1381 &clk_fixed_factor_ops, \ 1382 _flags), \ 1383 } 1384 1385 #ifdef CONFIG_OF 1386 int of_clk_add_provider(struct device_node *np, 1387 struct clk *(*clk_src_get)(struct of_phandle_args *args, 1388 void *data), 1389 void *data); 1390 int of_clk_add_hw_provider(struct device_node *np, 1391 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1392 void *data), 1393 void *data); 1394 int devm_of_clk_add_hw_provider(struct device *dev, 1395 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1396 void *data), 1397 void *data); 1398 void of_clk_del_provider(struct device_node *np); 1399 void devm_of_clk_del_provider(struct device *dev); 1400 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 1401 void *data); 1402 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, 1403 void *data); 1404 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 1405 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, 1406 void *data); 1407 int of_clk_parent_fill(struct device_node *np, const char **parents, 1408 unsigned int size); 1409 int of_clk_detect_critical(struct device_node *np, int index, 1410 unsigned long *flags); 1411 1412 #else /* !CONFIG_OF */ 1413 1414 static inline int of_clk_add_provider(struct device_node *np, 1415 struct clk *(*clk_src_get)(struct of_phandle_args *args, 1416 void *data), 1417 void *data) 1418 { 1419 return 0; 1420 } 1421 static inline int of_clk_add_hw_provider(struct device_node *np, 1422 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1423 void *data), 1424 void *data) 1425 { 1426 return 0; 1427 } 1428 static inline int devm_of_clk_add_hw_provider(struct device *dev, 1429 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1430 void *data), 1431 void *data) 1432 { 1433 return 0; 1434 } 1435 static inline void of_clk_del_provider(struct device_node *np) {} 1436 static inline void devm_of_clk_del_provider(struct device *dev) {} 1437 static inline struct clk *of_clk_src_simple_get( 1438 struct of_phandle_args *clkspec, void *data) 1439 { 1440 return ERR_PTR(-ENOENT); 1441 } 1442 static inline struct clk_hw * 1443 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) 1444 { 1445 return ERR_PTR(-ENOENT); 1446 } 1447 static inline struct clk *of_clk_src_onecell_get( 1448 struct of_phandle_args *clkspec, void *data) 1449 { 1450 return ERR_PTR(-ENOENT); 1451 } 1452 static inline struct clk_hw * 1453 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) 1454 { 1455 return ERR_PTR(-ENOENT); 1456 } 1457 static inline int of_clk_parent_fill(struct device_node *np, 1458 const char **parents, unsigned int size) 1459 { 1460 return 0; 1461 } 1462 static inline int of_clk_detect_critical(struct device_node *np, int index, 1463 unsigned long *flags) 1464 { 1465 return 0; 1466 } 1467 #endif /* CONFIG_OF */ 1468 1469 void clk_gate_restore_context(struct clk_hw *hw); 1470 1471 #endif /* CLK_PROVIDER_H */ 1472