1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_BRCMPHY_H 3 #define _LINUX_BRCMPHY_H 4 5 #include <linux/phy.h> 6 7 /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used 8 * to configure the switch internal registers via MDIO accesses. 9 */ 10 #define BRCM_PSEUDO_PHY_ADDR 30 11 12 #define PHY_ID_BCM50610 0x0143bd60 13 #define PHY_ID_BCM50610M 0x0143bd70 14 #define PHY_ID_BCM5241 0x0143bc30 15 #define PHY_ID_BCMAC131 0x0143bc70 16 #define PHY_ID_BCM5481 0x0143bca0 17 #define PHY_ID_BCM5395 0x0143bcf0 18 #define PHY_ID_BCM53125 0x03625f20 19 #define PHY_ID_BCM53128 0x03625e10 20 #define PHY_ID_BCM54810 0x03625d00 21 #define PHY_ID_BCM54811 0x03625cc0 22 #define PHY_ID_BCM5482 0x0143bcb0 23 #define PHY_ID_BCM5411 0x00206070 24 #define PHY_ID_BCM5421 0x002060e0 25 #define PHY_ID_BCM54210E 0x600d84a0 26 #define PHY_ID_BCM5464 0x002060b0 27 #define PHY_ID_BCM5461 0x002060c0 28 #define PHY_ID_BCM54612E 0x03625e60 29 #define PHY_ID_BCM54616S 0x03625d10 30 #define PHY_ID_BCM54140 0xae025009 31 #define PHY_ID_BCM57780 0x03625d90 32 #define PHY_ID_BCM89610 0x03625cd0 33 34 #define PHY_ID_BCM72113 0x35905310 35 #define PHY_ID_BCM72116 0x35905350 36 #define PHY_ID_BCM72165 0x35905340 37 #define PHY_ID_BCM7250 0xae025280 38 #define PHY_ID_BCM7255 0xae025120 39 #define PHY_ID_BCM7260 0xae025190 40 #define PHY_ID_BCM7268 0xae025090 41 #define PHY_ID_BCM7271 0xae0253b0 42 #define PHY_ID_BCM7278 0xae0251a0 43 #define PHY_ID_BCM7364 0xae025260 44 #define PHY_ID_BCM7366 0x600d8490 45 #define PHY_ID_BCM7346 0x600d8650 46 #define PHY_ID_BCM7362 0x600d84b0 47 #define PHY_ID_BCM7425 0x600d86b0 48 #define PHY_ID_BCM7429 0x600d8730 49 #define PHY_ID_BCM7435 0x600d8750 50 #define PHY_ID_BCM74371 0xae0252e0 51 #define PHY_ID_BCM7439 0x600d8480 52 #define PHY_ID_BCM7439_2 0xae025080 53 #define PHY_ID_BCM7445 0x600d8510 54 #define PHY_ID_BCM7712 0x35905330 55 56 #define PHY_ID_BCM_CYGNUS 0xae025200 57 #define PHY_ID_BCM_OMEGA 0xae025100 58 59 #define PHY_BCM_OUI_MASK 0xfffffc00 60 #define PHY_BCM_OUI_1 0x00206000 61 #define PHY_BCM_OUI_2 0x0143bc00 62 #define PHY_BCM_OUI_3 0x03625c00 63 #define PHY_BCM_OUI_4 0x600d8400 64 #define PHY_BCM_OUI_5 0x03625e00 65 #define PHY_BCM_OUI_6 0xae025000 66 67 #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000001 68 #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000002 69 #define PHY_BRCM_CLEAR_RGMII_MODE 0x00000004 70 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00000008 71 #define PHY_BRCM_EN_MASTER_MODE 0x00000010 72 #define PHY_BRCM_IDDQ_SUSPEND 0x00000020 73 74 /* Broadcom BCM7xxx specific workarounds */ 75 #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff) 76 #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff) 77 #define PHY_BCM_FLAGS_VALID 0x80000000 78 79 /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */ 80 #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */ 81 #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */ 82 #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */ 83 #define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIFO elasticity */ 84 85 #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */ 86 #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */ 87 88 #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ 89 #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ 90 #define MII_BCM54XX_EXP_SEL_TOP 0x0d00 /* TOP_MISC expansion register select */ 91 #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ 92 #define MII_BCM54XX_EXP_SEL_WOL 0x0e00 /* Wake-on-LAN expansion select register */ 93 #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ 94 #define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */ 95 96 #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */ 97 #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */ 98 #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */ 99 #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */ 100 #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */ 101 #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */ 102 #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */ 103 #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */ 104 #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */ 105 #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */ 106 #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */ 107 #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */ 108 #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */ 109 #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */ 110 #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */ 111 #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */ 112 #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */ 113 #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */ 114 115 #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ 116 #define MII_BCM54XX_SHD_WRITE 0x8000 117 #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) 118 #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) 119 120 #define MII_BCM54XX_RDB_ADDR 0x1e 121 #define MII_BCM54XX_RDB_DATA 0x1f 122 123 /* legacy access control via rdb/expansion register */ 124 #define BCM54XX_RDB_REG0087 0x0087 125 #define BCM54XX_EXP_REG7E (MII_BCM54XX_EXP_SEL_ER + 0x7E) 126 #define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15) 127 128 /* 129 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18) 130 */ 131 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00 132 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400 133 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800 134 #define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 0x4000 135 136 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07 137 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010 138 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080 139 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100 140 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200 141 #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000 142 143 #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12 144 #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007 145 146 /* 147 * Broadcom LED source encodings. These are used in BCM5461, BCM5481, 148 * BCM5482, and possibly some others. 149 */ 150 #define BCM_LED_SRC_LINKSPD1 0x0 151 #define BCM_LED_SRC_LINKSPD2 0x1 152 #define BCM_LED_SRC_XMITLED 0x2 153 #define BCM_LED_SRC_ACTIVITYLED 0x3 154 #define BCM_LED_SRC_FDXLED 0x4 155 #define BCM_LED_SRC_SLAVE 0x5 156 #define BCM_LED_SRC_INTR 0x6 157 #define BCM_LED_SRC_QUALITY 0x7 158 #define BCM_LED_SRC_RCVLED 0x8 159 #define BCM_LED_SRC_WIRESPEED 0x9 160 #define BCM_LED_SRC_MULTICOLOR1 0xa 161 #define BCM_LED_SRC_OPENSHORT 0xb 162 #define BCM_LED_SRC_OFF 0xe /* Tied high */ 163 #define BCM_LED_SRC_ON 0xf /* Tied low */ 164 165 /* 166 * Broadcom Multicolor LED configurations (expansion register 4) 167 */ 168 #define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04) 169 #define BCM_LED_MULTICOLOR_IN_PHASE BIT(8) 170 #define BCM_LED_MULTICOLOR_LINK_ACT 0x0 171 #define BCM_LED_MULTICOLOR_SPEED 0x1 172 #define BCM_LED_MULTICOLOR_ACT_FLASH 0x2 173 #define BCM_LED_MULTICOLOR_FDX 0x3 174 #define BCM_LED_MULTICOLOR_OFF 0x4 175 #define BCM_LED_MULTICOLOR_ON 0x5 176 #define BCM_LED_MULTICOLOR_ALT 0x6 177 #define BCM_LED_MULTICOLOR_FLASH 0x7 178 #define BCM_LED_MULTICOLOR_LINK 0x8 179 #define BCM_LED_MULTICOLOR_ACT 0x9 180 #define BCM_LED_MULTICOLOR_PROGRAM 0xa 181 182 /* 183 * BCM5482: Shadow registers 184 * Shadow values go into bits [14:10] of register 0x1c to select a shadow 185 * register to access. 186 */ 187 188 /* 00100: Reserved control register 2 */ 189 #define BCM54XX_SHD_SCR2 0x04 190 #define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100 191 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2 192 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2 193 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7 194 195 /* 00101: Spare Control Register 3 */ 196 #define BCM54XX_SHD_SCR3 0x05 197 #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001 198 #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002 199 #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004 200 #define BCM54XX_SHD_SCR3_RXCTXC_DIS 0x0100 201 202 /* 01010: Auto Power-Down */ 203 #define BCM54XX_SHD_APD 0x0a 204 #define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */ 205 #define BCM54XX_SHD_APD_EN 0x0020 206 #define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */ 207 #define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */ 208 209 #define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */ 210 /* LED3 / ~LINKSPD[2] selector */ 211 #define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4) 212 /* LED1 / ~LINKSPD[1] selector */ 213 #define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0) 214 #define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */ 215 #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */ 216 #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */ 217 #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */ 218 219 /* 10011: SerDes 100-FX Control Register */ 220 #define BCM54616S_SHD_100FX_CTRL 0x13 221 #define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */ 222 223 /* 11111: Mode Control Register */ 224 #define BCM54XX_SHD_MODE 0x1f 225 #define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */ 226 #define BCM54XX_SHD_INTF_SEL_RGMII 0x02 227 #define BCM54XX_SHD_INTF_SEL_SGMII 0x04 228 #define BCM54XX_SHD_INTF_SEL_GBIC 0x06 229 #define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */ 230 231 /* 232 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17) 233 */ 234 #define MII_BCM54XX_EXP_AADJ1CH0 0x001f 235 #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200 236 #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100 237 #define MII_BCM54XX_EXP_AADJ1CH3 0x601f 238 #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002 239 #define MII_BCM54XX_EXP_EXP08 0x0F08 240 #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001 241 #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200 242 #define MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE 0x0100 243 #define MII_BCM54XX_EXP_EXP75 0x0f75 244 #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c 245 #define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001 246 #define MII_BCM54XX_EXP_EXP96 0x0f96 247 #define MII_BCM54XX_EXP_EXP96_MYST 0x0010 248 #define MII_BCM54XX_EXP_EXP97 0x0f97 249 #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c 250 251 /* Top-MISC expansion registers */ 252 #define BCM54XX_TOP_MISC_IDDQ_CTRL (MII_BCM54XX_EXP_SEL_TOP + 0x06) 253 #define BCM54XX_TOP_MISC_IDDQ_LP (1 << 0) 254 #define BCM54XX_TOP_MISC_IDDQ_SD (1 << 2) 255 #define BCM54XX_TOP_MISC_IDDQ_SR (1 << 3) 256 257 #define BCM54XX_TOP_MISC_LED_CTL (MII_BCM54XX_EXP_SEL_TOP + 0x0C) 258 #define BCM54XX_LED4_SEL_INTR BIT(1) 259 260 /* 261 * BCM5482: Secondary SerDes registers 262 */ 263 #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */ 264 #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */ 265 #define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */ 266 #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */ 267 #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */ 268 269 /* BCM54810 Registers */ 270 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90) 271 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0) 272 #define BCM54810_SHD_CLK_CTL 0x3 273 #define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9) 274 275 /* BCM54612E Registers */ 276 #define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34) 277 #define BCM54612E_LED4_CLK125OUT_EN (1 << 1) 278 279 280 /* Wake-on-LAN registers */ 281 #define BCM54XX_WOL_MAIN_CTL (MII_BCM54XX_EXP_SEL_WOL + 0x80) 282 #define BCM54XX_WOL_EN BIT(0) 283 #define BCM54XX_WOL_MODE_SINGLE_MPD 0 284 #define BCM54XX_WOL_MODE_SINGLE_MPDSEC 1 285 #define BCM54XX_WOL_MODE_DUAL 2 286 #define BCM54XX_WOL_MODE_SHIFT 1 287 #define BCM54XX_WOL_MODE_MASK 0x3 288 #define BCM54XX_WOL_MP_MSB_FF_EN BIT(3) 289 #define BCM54XX_WOL_SECKEY_OPT_4B 0 290 #define BCM54XX_WOL_SECKEY_OPT_6B 1 291 #define BCM54XX_WOL_SECKEY_OPT_8B 2 292 #define BCM54XX_WOL_SECKEY_OPT_SHIFT 4 293 #define BCM54XX_WOL_SECKEY_OPT_MASK 0x3 294 #define BCM54XX_WOL_L2_TYPE_CHK BIT(6) 295 #define BCM54XX_WOL_L4IPV4UDP_CHK BIT(7) 296 #define BCM54XX_WOL_L4IPV6UDP_CHK BIT(8) 297 #define BCM54XX_WOL_UDPPORT_CHK BIT(9) 298 #define BCM54XX_WOL_CRC_CHK BIT(10) 299 #define BCM54XX_WOL_SECKEY_MODE BIT(11) 300 #define BCM54XX_WOL_RST BIT(12) 301 #define BCM54XX_WOL_DIR_PKT_EN BIT(13) 302 #define BCM54XX_WOL_MASK_MODE_DA_FF 0 303 #define BCM54XX_WOL_MASK_MODE_DA_MPD 1 304 #define BCM54XX_WOL_MASK_MODE_DA_ONLY 2 305 #define BCM54XX_WOL_MASK_MODE_MPD 3 306 #define BCM54XX_WOL_MASK_MODE_SHIFT 14 307 #define BCM54XX_WOL_MASK_MODE_MASK 0x3 308 309 #define BCM54XX_WOL_INNER_PROTO (MII_BCM54XX_EXP_SEL_WOL + 0x81) 310 #define BCM54XX_WOL_OUTER_PROTO (MII_BCM54XX_EXP_SEL_WOL + 0x82) 311 #define BCM54XX_WOL_OUTER_PROTO2 (MII_BCM54XX_EXP_SEL_WOL + 0x83) 312 313 #define BCM54XX_WOL_MPD_DATA1(x) (MII_BCM54XX_EXP_SEL_WOL + 0x84 + (x)) 314 #define BCM54XX_WOL_MPD_DATA2(x) (MII_BCM54XX_EXP_SEL_WOL + 0x87 + (x)) 315 #define BCM54XX_WOL_SEC_KEY_8B (MII_BCM54XX_EXP_SEL_WOL + 0x8A) 316 #define BCM54XX_WOL_MASK(x) (MII_BCM54XX_EXP_SEL_WOL + 0x8B + (x)) 317 #define BCM54XX_SEC_KEY_STORE(x) (MII_BCM54XX_EXP_SEL_WOL + 0x8E) 318 #define BCM54XX_WOL_SHARED_CNT (MII_BCM54XX_EXP_SEL_WOL + 0x92) 319 320 #define BCM54XX_WOL_INT_MASK (MII_BCM54XX_EXP_SEL_WOL + 0x93) 321 #define BCM54XX_WOL_PKT1 BIT(0) 322 #define BCM54XX_WOL_PKT2 BIT(1) 323 #define BCM54XX_WOL_DIR BIT(2) 324 #define BCM54XX_WOL_ALL_INTRS (BCM54XX_WOL_PKT1 | \ 325 BCM54XX_WOL_PKT2 | \ 326 BCM54XX_WOL_DIR) 327 328 #define BCM54XX_WOL_INT_STATUS (MII_BCM54XX_EXP_SEL_WOL + 0x94) 329 330 /*****************************************************************************/ 331 /* Fast Ethernet Transceiver definitions. */ 332 /*****************************************************************************/ 333 334 #define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */ 335 #define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */ 336 #define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */ 337 #define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */ 338 #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */ 339 #define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */ 340 341 #define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */ 342 #define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */ 343 344 345 /*** Shadow register definitions ***/ 346 347 #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */ 348 #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */ 349 350 #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */ 351 #define MII_BRCM_FET_SHDW_AM4_STANDBY 0x0008 /* Standby enable */ 352 #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003 353 #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001 354 355 #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */ 356 #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */ 357 358 #define BRCM_CL45VEN_EEE_CONTROL 0x803d 359 #define LPI_FEATURE_EN 0x8000 360 #define LPI_FEATURE_EN_DIG1000X 0x4000 361 362 /* Core register definitions*/ 363 #define MII_BRCM_CORE_BASE12 0x12 364 #define MII_BRCM_CORE_BASE13 0x13 365 #define MII_BRCM_CORE_BASE14 0x14 366 #define MII_BRCM_CORE_BASE1E 0x1E 367 #define MII_BRCM_CORE_EXPB0 0xB0 368 #define MII_BRCM_CORE_EXPB1 0xB1 369 370 /* Enhanced Cable Diagnostics */ 371 #define BCM54XX_RDB_ECD_CTRL 0x2a0 372 #define BCM54XX_EXP_ECD_CTRL (MII_BCM54XX_EXP_SEL_ER + 0xc0) 373 374 #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 1 /* CAT3 or worse */ 375 #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 0 /* CAT5 or better */ 376 #define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK BIT(0) /* cable type */ 377 #define BCM54XX_ECD_CTRL_INVALID BIT(3) /* invalid result */ 378 #define BCM54XX_ECD_CTRL_UNIT_CM 0 /* centimeters */ 379 #define BCM54XX_ECD_CTRL_UNIT_M 1 /* meters */ 380 #define BCM54XX_ECD_CTRL_UNIT_MASK BIT(10) /* cable length unit */ 381 #define BCM54XX_ECD_CTRL_IN_PROGRESS BIT(11) /* test in progress */ 382 #define BCM54XX_ECD_CTRL_BREAK_LINK BIT(12) /* unconnect link 383 * during test 384 */ 385 #define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS BIT(13) /* disable inter-pair 386 * short check 387 */ 388 #define BCM54XX_ECD_CTRL_RUN BIT(15) /* run immediate */ 389 390 #define BCM54XX_RDB_ECD_FAULT_TYPE 0x2a1 391 #define BCM54XX_EXP_ECD_FAULT_TYPE (MII_BCM54XX_EXP_SEL_ER + 0xc1) 392 #define BCM54XX_ECD_FAULT_TYPE_INVALID 0x0 393 #define BCM54XX_ECD_FAULT_TYPE_OK 0x1 394 #define BCM54XX_ECD_FAULT_TYPE_OPEN 0x2 395 #define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 0x3 /* short same pair */ 396 #define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 0x4 /* short different pairs */ 397 #define BCM54XX_ECD_FAULT_TYPE_BUSY 0x9 398 #define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0) 399 #define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4) 400 #define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8) 401 #define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12) 402 #define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 0x2a2 403 #define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 0x2a3 404 #define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 0x2a4 405 #define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 0x2a5 406 407 #define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 0x2a2 408 #define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc2) 409 #define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 0x2a3 410 #define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc3) 411 #define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 0x2a4 412 #define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc4) 413 #define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 0x2a5 414 #define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc5) 415 #define BCM54XX_ECD_LENGTH_RESULTS_INVALID 0xffff 416 417 #endif /* _LINUX_BRCMPHY_H */ 418