1 #ifndef _LINUX_BRCMPHY_H 2 #define _LINUX_BRCMPHY_H 3 4 #include <linux/phy.h> 5 6 /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used 7 * to configure the switch internal registers via MDIO accesses. 8 */ 9 #define BRCM_PSEUDO_PHY_ADDR 30 10 11 #define PHY_ID_BCM50610 0x0143bd60 12 #define PHY_ID_BCM50610M 0x0143bd70 13 #define PHY_ID_BCM5241 0x0143bc30 14 #define PHY_ID_BCMAC131 0x0143bc70 15 #define PHY_ID_BCM5481 0x0143bca0 16 #define PHY_ID_BCM5482 0x0143bcb0 17 #define PHY_ID_BCM5411 0x00206070 18 #define PHY_ID_BCM5421 0x002060e0 19 #define PHY_ID_BCM5464 0x002060b0 20 #define PHY_ID_BCM5461 0x002060c0 21 #define PHY_ID_BCM54616S 0x03625d10 22 #define PHY_ID_BCM57780 0x03625d90 23 24 #define PHY_ID_BCM7250 0xae025280 25 #define PHY_ID_BCM7364 0xae025260 26 #define PHY_ID_BCM7366 0x600d8490 27 #define PHY_ID_BCM7346 0x600d8650 28 #define PHY_ID_BCM7362 0x600d84b0 29 #define PHY_ID_BCM7425 0x600d86b0 30 #define PHY_ID_BCM7429 0x600d8730 31 #define PHY_ID_BCM7435 0x600d8750 32 #define PHY_ID_BCM7439 0x600d8480 33 #define PHY_ID_BCM7439_2 0xae025080 34 #define PHY_ID_BCM7445 0x600d8510 35 36 #define PHY_ID_BCM_CYGNUS 0xae025200 37 38 #define PHY_BCM_OUI_MASK 0xfffffc00 39 #define PHY_BCM_OUI_1 0x00206000 40 #define PHY_BCM_OUI_2 0x0143bc00 41 #define PHY_BCM_OUI_3 0x03625c00 42 #define PHY_BCM_OUI_4 0x600d8400 43 #define PHY_BCM_OUI_5 0x03625e00 44 #define PHY_BCM_OUI_6 0xae025000 45 46 #define PHY_BCM_FLAGS_MODE_COPPER 0x00000001 47 #define PHY_BCM_FLAGS_MODE_1000BX 0x00000002 48 #define PHY_BCM_FLAGS_INTF_SGMII 0x00000010 49 #define PHY_BCM_FLAGS_INTF_XAUI 0x00000020 50 #define PHY_BRCM_WIRESPEED_ENABLE 0x00000100 51 #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200 52 #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400 53 #define PHY_BRCM_STD_IBND_DISABLE 0x00000800 54 #define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000 55 #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000 56 #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000 57 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000 58 /* Broadcom BCM7xxx specific workarounds */ 59 #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff) 60 #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff) 61 #define PHY_BCM_FLAGS_VALID 0x80000000 62 63 /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */ 64 #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */ 65 #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */ 66 #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */ 67 68 #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */ 69 #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */ 70 71 #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ 72 #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ 73 #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ 74 #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ 75 76 #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */ 77 #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */ 78 #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */ 79 #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */ 80 #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */ 81 #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */ 82 #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */ 83 #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */ 84 #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */ 85 #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */ 86 #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */ 87 #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */ 88 #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */ 89 #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */ 90 #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */ 91 #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */ 92 #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */ 93 #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */ 94 95 #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ 96 #define MII_BCM54XX_SHD_WRITE 0x8000 97 #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) 98 #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) 99 100 /* 101 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18) 102 */ 103 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000 104 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400 105 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800 106 107 #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000 108 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200 109 #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000 110 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007 111 112 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000 113 114 /* 115 * Broadcom LED source encodings. These are used in BCM5461, BCM5481, 116 * BCM5482, and possibly some others. 117 */ 118 #define BCM_LED_SRC_LINKSPD1 0x0 119 #define BCM_LED_SRC_LINKSPD2 0x1 120 #define BCM_LED_SRC_XMITLED 0x2 121 #define BCM_LED_SRC_ACTIVITYLED 0x3 122 #define BCM_LED_SRC_FDXLED 0x4 123 #define BCM_LED_SRC_SLAVE 0x5 124 #define BCM_LED_SRC_INTR 0x6 125 #define BCM_LED_SRC_QUALITY 0x7 126 #define BCM_LED_SRC_RCVLED 0x8 127 #define BCM_LED_SRC_MULTICOLOR1 0xa 128 #define BCM_LED_SRC_OPENSHORT 0xb 129 #define BCM_LED_SRC_OFF 0xe /* Tied high */ 130 #define BCM_LED_SRC_ON 0xf /* Tied low */ 131 132 133 /* 134 * BCM5482: Shadow registers 135 * Shadow values go into bits [14:10] of register 0x1c to select a shadow 136 * register to access. 137 */ 138 /* 00101: Spare Control Register 3 */ 139 #define BCM54XX_SHD_SCR3 0x05 140 #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001 141 #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002 142 #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004 143 144 /* 01010: Auto Power-Down */ 145 #define BCM54XX_SHD_APD 0x0a 146 #define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */ 147 #define BCM54XX_SHD_APD_EN 0x0020 148 #define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */ 149 #define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */ 150 151 #define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */ 152 /* LED3 / ~LINKSPD[2] selector */ 153 #define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4) 154 /* LED1 / ~LINKSPD[1] selector */ 155 #define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0) 156 #define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */ 157 #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */ 158 #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */ 159 #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */ 160 #define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */ 161 #define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */ 162 163 164 /* 165 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17) 166 */ 167 #define MII_BCM54XX_EXP_AADJ1CH0 0x001f 168 #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200 169 #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100 170 #define MII_BCM54XX_EXP_AADJ1CH3 0x601f 171 #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002 172 #define MII_BCM54XX_EXP_EXP08 0x0F08 173 #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001 174 #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200 175 #define MII_BCM54XX_EXP_EXP75 0x0f75 176 #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c 177 #define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001 178 #define MII_BCM54XX_EXP_EXP96 0x0f96 179 #define MII_BCM54XX_EXP_EXP96_MYST 0x0010 180 #define MII_BCM54XX_EXP_EXP97 0x0f97 181 #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c 182 183 /* 184 * BCM5482: Secondary SerDes registers 185 */ 186 #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */ 187 #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */ 188 #define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */ 189 #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */ 190 #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */ 191 192 193 /*****************************************************************************/ 194 /* Fast Ethernet Transceiver definitions. */ 195 /*****************************************************************************/ 196 197 #define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */ 198 #define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */ 199 #define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */ 200 #define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */ 201 #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */ 202 #define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */ 203 204 #define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */ 205 #define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */ 206 207 208 /*** Shadow register definitions ***/ 209 210 #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */ 211 #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */ 212 213 #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */ 214 #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003 215 #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001 216 217 #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */ 218 #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */ 219 220 #define BRCM_CL45VEN_EEE_CONTROL 0x803d 221 #define LPI_FEATURE_EN 0x8000 222 #define LPI_FEATURE_EN_DIG1000X 0x4000 223 224 /* Core register definitions*/ 225 #define MII_BRCM_CORE_BASE1E 0x1E 226 #define MII_BRCM_CORE_EXPB0 0xB0 227 #define MII_BRCM_CORE_EXPB1 0xB1 228 229 #endif /* _LINUX_BRCMPHY_H */ 230