1 #ifndef _LINUX_BRCMPHY_H 2 #define _LINUX_BRCMPHY_H 3 4 #define PHY_ID_BCM50610 0x0143bd60 5 #define PHY_ID_BCM50610M 0x0143bd70 6 #define PHY_ID_BCM5241 0x0143bc30 7 #define PHY_ID_BCMAC131 0x0143bc70 8 #define PHY_ID_BCM5481 0x0143bca0 9 #define PHY_ID_BCM5482 0x0143bcb0 10 #define PHY_ID_BCM5411 0x00206070 11 #define PHY_ID_BCM5421 0x002060e0 12 #define PHY_ID_BCM5464 0x002060b0 13 #define PHY_ID_BCM5461 0x002060c0 14 #define PHY_ID_BCM57780 0x03625d90 15 16 #define PHY_ID_BCM7366 0x600d8490 17 #define PHY_ID_BCM7439 0x600d8480 18 #define PHY_ID_BCM7445 0x600d8510 19 #define PHY_ID_BCM7XXX_28 0x600d8400 20 21 #define PHY_BCM_OUI_MASK 0xfffffc00 22 #define PHY_BCM_OUI_1 0x00206000 23 #define PHY_BCM_OUI_2 0x0143bc00 24 #define PHY_BCM_OUI_3 0x03625c00 25 #define PHY_BCM_OUI_4 0x600d0000 26 #define PHY_BCM_OUI_5 0x03625e00 27 28 29 #define PHY_BCM_FLAGS_MODE_COPPER 0x00000001 30 #define PHY_BCM_FLAGS_MODE_1000BX 0x00000002 31 #define PHY_BCM_FLAGS_INTF_SGMII 0x00000010 32 #define PHY_BCM_FLAGS_INTF_XAUI 0x00000020 33 #define PHY_BRCM_WIRESPEED_ENABLE 0x00000100 34 #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200 35 #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400 36 #define PHY_BRCM_STD_IBND_DISABLE 0x00000800 37 #define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000 38 #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000 39 #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000 40 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000 41 /* Broadcom BCM7xxx specific workarounds */ 42 #define PHY_BRCM_100MBPS_WAR 0x00010000 43 #define PHY_BCM_FLAGS_VALID 0x80000000 44 45 /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */ 46 #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */ 47 #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */ 48 #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */ 49 50 #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */ 51 #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */ 52 53 #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ 54 #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ 55 #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ 56 #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ 57 58 #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */ 59 #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */ 60 #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */ 61 #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */ 62 #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */ 63 #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */ 64 #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */ 65 #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */ 66 #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */ 67 #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */ 68 #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */ 69 #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */ 70 #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */ 71 #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */ 72 #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */ 73 #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */ 74 #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */ 75 #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */ 76 77 #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ 78 #define MII_BCM54XX_SHD_WRITE 0x8000 79 #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) 80 #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) 81 82 /* 83 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18) 84 */ 85 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000 86 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400 87 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800 88 89 #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000 90 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200 91 #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000 92 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007 93 94 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000 95 96 #endif /* _LINUX_BRCMPHY_H */ 97