1*da660b4aSCatalin Marinas /* 2*da660b4aSCatalin Marinas * arch/arm/include/asm/hardware/sp810.h 3*da660b4aSCatalin Marinas * 4*da660b4aSCatalin Marinas * ARM PrimeXsys System Controller SP810 header file 5*da660b4aSCatalin Marinas * 6*da660b4aSCatalin Marinas * Copyright (C) 2009 ST Microelectronics 7*da660b4aSCatalin Marinas * Viresh Kumar <viresh.linux@gmail.com> 8*da660b4aSCatalin Marinas * 9*da660b4aSCatalin Marinas * This file is licensed under the terms of the GNU General Public 10*da660b4aSCatalin Marinas * License version 2. This program is licensed "as is" without any 11*da660b4aSCatalin Marinas * warranty of any kind, whether express or implied. 12*da660b4aSCatalin Marinas */ 13*da660b4aSCatalin Marinas 14*da660b4aSCatalin Marinas #ifndef __ASM_ARM_SP810_H 15*da660b4aSCatalin Marinas #define __ASM_ARM_SP810_H 16*da660b4aSCatalin Marinas 17*da660b4aSCatalin Marinas #include <linux/io.h> 18*da660b4aSCatalin Marinas 19*da660b4aSCatalin Marinas /* sysctl registers offset */ 20*da660b4aSCatalin Marinas #define SCCTRL 0x000 21*da660b4aSCatalin Marinas #define SCSYSSTAT 0x004 22*da660b4aSCatalin Marinas #define SCIMCTRL 0x008 23*da660b4aSCatalin Marinas #define SCIMSTAT 0x00C 24*da660b4aSCatalin Marinas #define SCXTALCTRL 0x010 25*da660b4aSCatalin Marinas #define SCPLLCTRL 0x014 26*da660b4aSCatalin Marinas #define SCPLLFCTRL 0x018 27*da660b4aSCatalin Marinas #define SCPERCTRL0 0x01C 28*da660b4aSCatalin Marinas #define SCPERCTRL1 0x020 29*da660b4aSCatalin Marinas #define SCPEREN 0x024 30*da660b4aSCatalin Marinas #define SCPERDIS 0x028 31*da660b4aSCatalin Marinas #define SCPERCLKEN 0x02C 32*da660b4aSCatalin Marinas #define SCPERSTAT 0x030 33*da660b4aSCatalin Marinas #define SCSYSID0 0xEE0 34*da660b4aSCatalin Marinas #define SCSYSID1 0xEE4 35*da660b4aSCatalin Marinas #define SCSYSID2 0xEE8 36*da660b4aSCatalin Marinas #define SCSYSID3 0xEEC 37*da660b4aSCatalin Marinas #define SCITCR 0xF00 38*da660b4aSCatalin Marinas #define SCITIR0 0xF04 39*da660b4aSCatalin Marinas #define SCITIR1 0xF08 40*da660b4aSCatalin Marinas #define SCITOR 0xF0C 41*da660b4aSCatalin Marinas #define SCCNTCTRL 0xF10 42*da660b4aSCatalin Marinas #define SCCNTDATA 0xF14 43*da660b4aSCatalin Marinas #define SCCNTSTEP 0xF18 44*da660b4aSCatalin Marinas #define SCPERIPHID0 0xFE0 45*da660b4aSCatalin Marinas #define SCPERIPHID1 0xFE4 46*da660b4aSCatalin Marinas #define SCPERIPHID2 0xFE8 47*da660b4aSCatalin Marinas #define SCPERIPHID3 0xFEC 48*da660b4aSCatalin Marinas #define SCPCELLID0 0xFF0 49*da660b4aSCatalin Marinas #define SCPCELLID1 0xFF4 50*da660b4aSCatalin Marinas #define SCPCELLID2 0xFF8 51*da660b4aSCatalin Marinas #define SCPCELLID3 0xFFC 52*da660b4aSCatalin Marinas 53*da660b4aSCatalin Marinas #define SCCTRL_TIMERENnSEL_SHIFT(n) (15 + ((n) * 2)) 54*da660b4aSCatalin Marinas 55*da660b4aSCatalin Marinas static inline void sysctl_soft_reset(void __iomem *base) 56*da660b4aSCatalin Marinas { 57*da660b4aSCatalin Marinas /* switch to slow mode */ 58*da660b4aSCatalin Marinas writel(0x2, base + SCCTRL); 59*da660b4aSCatalin Marinas 60*da660b4aSCatalin Marinas /* writing any value to SCSYSSTAT reg will reset system */ 61*da660b4aSCatalin Marinas writel(0, base + SCSYSSTAT); 62*da660b4aSCatalin Marinas } 63*da660b4aSCatalin Marinas 64*da660b4aSCatalin Marinas #endif /* __ASM_ARM_SP810_H */ 65