1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015, 2016 ARM Ltd. 4 */ 5 #ifndef __KVM_ARM_VGIC_H 6 #define __KVM_ARM_VGIC_H 7 8 #include <linux/kernel.h> 9 #include <linux/kvm.h> 10 #include <linux/irqreturn.h> 11 #include <linux/spinlock.h> 12 #include <linux/static_key.h> 13 #include <linux/types.h> 14 #include <kvm/iodev.h> 15 #include <linux/list.h> 16 #include <linux/jump_label.h> 17 18 #include <linux/irqchip/arm-gic-v4.h> 19 20 #define VGIC_V3_MAX_CPUS 512 21 #define VGIC_V2_MAX_CPUS 8 22 #define VGIC_NR_IRQS_LEGACY 256 23 #define VGIC_NR_SGIS 16 24 #define VGIC_NR_PPIS 16 25 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 26 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) 27 #define VGIC_MAX_SPI 1019 28 #define VGIC_MAX_RESERVED 1023 29 #define VGIC_MIN_LPI 8192 30 #define KVM_IRQCHIP_NUM_PINS (1020 - 32) 31 32 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS) 33 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \ 34 (irq) <= VGIC_MAX_SPI) 35 36 enum vgic_type { 37 VGIC_V2, /* Good ol' GICv2 */ 38 VGIC_V3, /* New fancy GICv3 */ 39 }; 40 41 /* same for all guests, as depending only on the _host's_ GIC model */ 42 struct vgic_global { 43 /* type of the host GIC */ 44 enum vgic_type type; 45 46 /* Physical address of vgic virtual cpu interface */ 47 phys_addr_t vcpu_base; 48 49 /* GICV mapping, kernel VA */ 50 void __iomem *vcpu_base_va; 51 /* GICV mapping, HYP VA */ 52 void __iomem *vcpu_hyp_va; 53 54 /* virtual control interface mapping, kernel VA */ 55 void __iomem *vctrl_base; 56 /* virtual control interface mapping, HYP VA */ 57 void __iomem *vctrl_hyp; 58 59 /* Number of implemented list registers */ 60 int nr_lr; 61 62 /* Maintenance IRQ number */ 63 unsigned int maint_irq; 64 65 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */ 66 int max_gic_vcpus; 67 68 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 69 bool can_emulate_gicv2; 70 71 /* Hardware has GICv4? */ 72 bool has_gicv4; 73 bool has_gicv4_1; 74 75 /* Pseudo GICv3 from outer space */ 76 bool no_hw_deactivation; 77 78 /* GIC system register CPU interface */ 79 struct static_key_false gicv3_cpuif; 80 81 u32 ich_vtr_el2; 82 }; 83 84 extern struct vgic_global kvm_vgic_global_state; 85 86 #define VGIC_V2_MAX_LRS (1 << 6) 87 #define VGIC_V3_MAX_LRS 16 88 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) 89 90 enum vgic_irq_config { 91 VGIC_CONFIG_EDGE = 0, 92 VGIC_CONFIG_LEVEL 93 }; 94 95 /* 96 * Per-irq ops overriding some common behavious. 97 * 98 * Always called in non-preemptible section and the functions can use 99 * kvm_arm_get_running_vcpu() to get the vcpu pointer for private IRQs. 100 */ 101 struct irq_ops { 102 /* Per interrupt flags for special-cased interrupts */ 103 unsigned long flags; 104 105 #define VGIC_IRQ_SW_RESAMPLE BIT(0) /* Clear the active state for resampling */ 106 107 /* 108 * Callback function pointer to in-kernel devices that can tell us the 109 * state of the input level of mapped level-triggered IRQ faster than 110 * peaking into the physical GIC. 111 */ 112 bool (*get_input_level)(int vintid); 113 }; 114 115 struct vgic_irq { 116 raw_spinlock_t irq_lock; /* Protects the content of the struct */ 117 struct list_head lpi_list; /* Used to link all LPIs together */ 118 struct list_head ap_list; 119 120 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU 121 * SPIs and LPIs: The VCPU whose ap_list 122 * this is queued on. 123 */ 124 125 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should 126 * be sent to, as a result of the 127 * targets reg (v2) or the 128 * affinity reg (v3). 129 */ 130 131 u32 intid; /* Guest visible INTID */ 132 bool line_level; /* Level only */ 133 bool pending_latch; /* The pending latch state used to calculate 134 * the pending state for both level 135 * and edge triggered IRQs. */ 136 bool active; /* not used for LPIs */ 137 bool enabled; 138 bool hw; /* Tied to HW IRQ */ 139 struct kref refcount; /* Used for LPIs */ 140 u32 hwintid; /* HW INTID number */ 141 unsigned int host_irq; /* linux irq corresponding to hwintid */ 142 union { 143 u8 targets; /* GICv2 target VCPUs mask */ 144 u32 mpidr; /* GICv3 target VCPU */ 145 }; 146 u8 source; /* GICv2 SGIs only */ 147 u8 active_source; /* GICv2 SGIs only */ 148 u8 priority; 149 u8 group; /* 0 == group 0, 1 == group 1 */ 150 enum vgic_irq_config config; /* Level or edge */ 151 152 struct irq_ops *ops; 153 154 void *owner; /* Opaque pointer to reserve an interrupt 155 for in-kernel devices. */ 156 }; 157 158 static inline bool vgic_irq_needs_resampling(struct vgic_irq *irq) 159 { 160 return irq->ops && (irq->ops->flags & VGIC_IRQ_SW_RESAMPLE); 161 } 162 163 struct vgic_register_region; 164 struct vgic_its; 165 166 enum iodev_type { 167 IODEV_CPUIF, 168 IODEV_DIST, 169 IODEV_REDIST, 170 IODEV_ITS 171 }; 172 173 struct vgic_io_device { 174 gpa_t base_addr; 175 union { 176 struct kvm_vcpu *redist_vcpu; 177 struct vgic_its *its; 178 }; 179 const struct vgic_register_region *regions; 180 enum iodev_type iodev_type; 181 int nr_regions; 182 struct kvm_io_device dev; 183 }; 184 185 struct vgic_its { 186 /* The base address of the ITS control register frame */ 187 gpa_t vgic_its_base; 188 189 bool enabled; 190 struct vgic_io_device iodev; 191 struct kvm_device *dev; 192 193 /* These registers correspond to GITS_BASER{0,1} */ 194 u64 baser_device_table; 195 u64 baser_coll_table; 196 197 /* Protects the command queue */ 198 struct mutex cmd_lock; 199 u64 cbaser; 200 u32 creadr; 201 u32 cwriter; 202 203 /* migration ABI revision in use */ 204 u32 abi_rev; 205 206 /* Protects the device and collection lists */ 207 struct mutex its_lock; 208 struct list_head device_list; 209 struct list_head collection_list; 210 }; 211 212 struct vgic_state_iter; 213 214 struct vgic_redist_region { 215 u32 index; 216 gpa_t base; 217 u32 count; /* number of redistributors or 0 if single region */ 218 u32 free_index; /* index of the next free redistributor */ 219 struct list_head list; 220 }; 221 222 struct vgic_dist { 223 bool in_kernel; 224 bool ready; 225 bool initialized; 226 227 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 228 u32 vgic_model; 229 230 /* Implementation revision as reported in the GICD_IIDR */ 231 u32 implementation_rev; 232 233 /* Userspace can write to GICv2 IGROUPR */ 234 bool v2_groups_user_writable; 235 236 /* Do injected MSIs require an additional device ID? */ 237 bool msis_require_devid; 238 239 int nr_spis; 240 241 /* base addresses in guest physical address space: */ 242 gpa_t vgic_dist_base; /* distributor */ 243 union { 244 /* either a GICv2 CPU interface */ 245 gpa_t vgic_cpu_base; 246 /* or a number of GICv3 redistributor regions */ 247 struct list_head rd_regions; 248 }; 249 250 /* distributor enabled */ 251 bool enabled; 252 253 /* Wants SGIs without active state */ 254 bool nassgireq; 255 256 struct vgic_irq *spis; 257 258 struct vgic_io_device dist_iodev; 259 260 bool has_its; 261 262 /* 263 * Contains the attributes and gpa of the LPI configuration table. 264 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share 265 * one address across all redistributors. 266 * GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables" 267 */ 268 u64 propbaser; 269 270 /* Protects the lpi_list and the count value below. */ 271 raw_spinlock_t lpi_list_lock; 272 struct list_head lpi_list_head; 273 int lpi_list_count; 274 275 /* LPI translation cache */ 276 struct list_head lpi_translation_cache; 277 278 /* used by vgic-debug */ 279 struct vgic_state_iter *iter; 280 281 /* 282 * GICv4 ITS per-VM data, containing the IRQ domain, the VPE 283 * array, the property table pointer as well as allocation 284 * data. This essentially ties the Linux IRQ core and ITS 285 * together, and avoids leaking KVM's data structures anywhere 286 * else. 287 */ 288 struct its_vm its_vm; 289 }; 290 291 struct vgic_v2_cpu_if { 292 u32 vgic_hcr; 293 u32 vgic_vmcr; 294 u32 vgic_apr; 295 u32 vgic_lr[VGIC_V2_MAX_LRS]; 296 297 unsigned int used_lrs; 298 }; 299 300 struct vgic_v3_cpu_if { 301 u32 vgic_hcr; 302 u32 vgic_vmcr; 303 u32 vgic_sre; /* Restored only, change ignored */ 304 u32 vgic_ap0r[4]; 305 u32 vgic_ap1r[4]; 306 u64 vgic_lr[VGIC_V3_MAX_LRS]; 307 308 /* 309 * GICv4 ITS per-VPE data, containing the doorbell IRQ, the 310 * pending table pointer, the its_vm pointer and a few other 311 * HW specific things. As for the its_vm structure, this is 312 * linking the Linux IRQ subsystem and the ITS together. 313 */ 314 struct its_vpe its_vpe; 315 316 unsigned int used_lrs; 317 }; 318 319 struct vgic_cpu { 320 /* CPU vif control registers for world switch */ 321 union { 322 struct vgic_v2_cpu_if vgic_v2; 323 struct vgic_v3_cpu_if vgic_v3; 324 }; 325 326 struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; 327 328 raw_spinlock_t ap_list_lock; /* Protects the ap_list */ 329 330 /* 331 * List of IRQs that this VCPU should consider because they are either 332 * Active or Pending (hence the name; AP list), or because they recently 333 * were one of the two and need to be migrated off this list to another 334 * VCPU. 335 */ 336 struct list_head ap_list_head; 337 338 /* 339 * Members below are used with GICv3 emulation only and represent 340 * parts of the redistributor. 341 */ 342 struct vgic_io_device rd_iodev; 343 struct vgic_redist_region *rdreg; 344 u32 rdreg_index; 345 346 /* Contains the attributes and gpa of the LPI pending tables. */ 347 u64 pendbaser; 348 349 bool lpis_enabled; 350 351 /* Cache guest priority bits */ 352 u32 num_pri_bits; 353 354 /* Cache guest interrupt ID bits */ 355 u32 num_id_bits; 356 }; 357 358 extern struct static_key_false vgic_v2_cpuif_trap; 359 extern struct static_key_false vgic_v3_cpuif_trap; 360 361 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); 362 void kvm_vgic_early_init(struct kvm *kvm); 363 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); 364 int kvm_vgic_create(struct kvm *kvm, u32 type); 365 void kvm_vgic_destroy(struct kvm *kvm); 366 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 367 int kvm_vgic_map_resources(struct kvm *kvm); 368 int kvm_vgic_hyp_init(void); 369 void kvm_vgic_init_cpu_hardware(void); 370 371 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid, 372 bool level, void *owner); 373 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq, 374 u32 vintid, struct irq_ops *ops); 375 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid); 376 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid); 377 378 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 379 380 void kvm_vgic_load(struct kvm_vcpu *vcpu); 381 void kvm_vgic_put(struct kvm_vcpu *vcpu); 382 void kvm_vgic_vmcr_sync(struct kvm_vcpu *vcpu); 383 384 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 385 #define vgic_initialized(k) ((k)->arch.vgic.initialized) 386 #define vgic_ready(k) ((k)->arch.vgic.ready) 387 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ 388 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) 389 390 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu); 391 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 392 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 393 void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid); 394 395 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1); 396 397 /** 398 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW 399 * 400 * The host's GIC naturally limits the maximum amount of VCPUs a guest 401 * can use. 402 */ 403 static inline int kvm_vgic_get_max_vcpus(void) 404 { 405 return kvm_vgic_global_state.max_gic_vcpus; 406 } 407 408 /** 409 * kvm_vgic_setup_default_irq_routing: 410 * Setup a default flat gsi routing table mapping all SPIs 411 */ 412 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm); 413 414 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner); 415 416 struct kvm_kernel_irq_routing_entry; 417 418 int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq, 419 struct kvm_kernel_irq_routing_entry *irq_entry); 420 421 int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq, 422 struct kvm_kernel_irq_routing_entry *irq_entry); 423 424 int vgic_v4_load(struct kvm_vcpu *vcpu); 425 void vgic_v4_commit(struct kvm_vcpu *vcpu); 426 int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db); 427 428 #endif /* __KVM_ARM_VGIC_H */ 429