1 /* 2 * Copyright (C) 2015, 2016 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __KVM_ARM_VGIC_H 17 #define __KVM_ARM_VGIC_H 18 19 #include <linux/kernel.h> 20 #include <linux/kvm.h> 21 #include <linux/irqreturn.h> 22 #include <linux/spinlock.h> 23 #include <linux/types.h> 24 #include <kvm/iodev.h> 25 26 #define VGIC_V3_MAX_CPUS 255 27 #define VGIC_V2_MAX_CPUS 8 28 #define VGIC_NR_IRQS_LEGACY 256 29 #define VGIC_NR_SGIS 16 30 #define VGIC_NR_PPIS 16 31 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 32 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) 33 #define VGIC_MAX_SPI 1019 34 #define VGIC_MAX_RESERVED 1023 35 #define VGIC_MIN_LPI 8192 36 37 enum vgic_type { 38 VGIC_V2, /* Good ol' GICv2 */ 39 VGIC_V3, /* New fancy GICv3 */ 40 }; 41 42 /* same for all guests, as depending only on the _host's_ GIC model */ 43 struct vgic_global { 44 /* type of the host GIC */ 45 enum vgic_type type; 46 47 /* Physical address of vgic virtual cpu interface */ 48 phys_addr_t vcpu_base; 49 50 /* virtual control interface mapping */ 51 void __iomem *vctrl_base; 52 53 /* Number of implemented list registers */ 54 int nr_lr; 55 56 /* Maintenance IRQ number */ 57 unsigned int maint_irq; 58 59 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */ 60 int max_gic_vcpus; 61 62 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 63 bool can_emulate_gicv2; 64 }; 65 66 extern struct vgic_global kvm_vgic_global_state; 67 68 #define VGIC_V2_MAX_LRS (1 << 6) 69 #define VGIC_V3_MAX_LRS 16 70 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) 71 72 enum vgic_irq_config { 73 VGIC_CONFIG_EDGE = 0, 74 VGIC_CONFIG_LEVEL 75 }; 76 77 struct vgic_irq { 78 spinlock_t irq_lock; /* Protects the content of the struct */ 79 struct list_head ap_list; 80 81 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU 82 * SPIs and LPIs: The VCPU whose ap_list 83 * this is queued on. 84 */ 85 86 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should 87 * be sent to, as a result of the 88 * targets reg (v2) or the 89 * affinity reg (v3). 90 */ 91 92 u32 intid; /* Guest visible INTID */ 93 bool pending; 94 bool line_level; /* Level only */ 95 bool soft_pending; /* Level only */ 96 bool active; /* not used for LPIs */ 97 bool enabled; 98 bool hw; /* Tied to HW IRQ */ 99 u32 hwintid; /* HW INTID number */ 100 union { 101 u8 targets; /* GICv2 target VCPUs mask */ 102 u32 mpidr; /* GICv3 target VCPU */ 103 }; 104 u8 source; /* GICv2 SGIs only */ 105 u8 priority; 106 enum vgic_irq_config config; /* Level or edge */ 107 }; 108 109 struct vgic_register_region; 110 111 struct vgic_io_device { 112 gpa_t base_addr; 113 struct kvm_vcpu *redist_vcpu; 114 const struct vgic_register_region *regions; 115 int nr_regions; 116 struct kvm_io_device dev; 117 }; 118 119 struct vgic_dist { 120 bool in_kernel; 121 bool ready; 122 bool initialized; 123 124 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 125 u32 vgic_model; 126 127 int nr_spis; 128 129 /* TODO: Consider moving to global state */ 130 /* Virtual control interface mapping */ 131 void __iomem *vctrl_base; 132 133 /* base addresses in guest physical address space: */ 134 gpa_t vgic_dist_base; /* distributor */ 135 union { 136 /* either a GICv2 CPU interface */ 137 gpa_t vgic_cpu_base; 138 /* or a number of GICv3 redistributor regions */ 139 gpa_t vgic_redist_base; 140 }; 141 142 /* distributor enabled */ 143 bool enabled; 144 145 struct vgic_irq *spis; 146 147 struct vgic_io_device dist_iodev; 148 }; 149 150 struct vgic_v2_cpu_if { 151 u32 vgic_hcr; 152 u32 vgic_vmcr; 153 u32 vgic_misr; /* Saved only */ 154 u64 vgic_eisr; /* Saved only */ 155 u64 vgic_elrsr; /* Saved only */ 156 u32 vgic_apr; 157 u32 vgic_lr[VGIC_V2_MAX_LRS]; 158 }; 159 160 struct vgic_v3_cpu_if { 161 #ifdef CONFIG_KVM_ARM_VGIC_V3 162 u32 vgic_hcr; 163 u32 vgic_vmcr; 164 u32 vgic_sre; /* Restored only, change ignored */ 165 u32 vgic_misr; /* Saved only */ 166 u32 vgic_eisr; /* Saved only */ 167 u32 vgic_elrsr; /* Saved only */ 168 u32 vgic_ap0r[4]; 169 u32 vgic_ap1r[4]; 170 u64 vgic_lr[VGIC_V3_MAX_LRS]; 171 #endif 172 }; 173 174 struct vgic_cpu { 175 /* CPU vif control registers for world switch */ 176 union { 177 struct vgic_v2_cpu_if vgic_v2; 178 struct vgic_v3_cpu_if vgic_v3; 179 }; 180 181 unsigned int used_lrs; 182 struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; 183 184 spinlock_t ap_list_lock; /* Protects the ap_list */ 185 186 /* 187 * List of IRQs that this VCPU should consider because they are either 188 * Active or Pending (hence the name; AP list), or because they recently 189 * were one of the two and need to be migrated off this list to another 190 * VCPU. 191 */ 192 struct list_head ap_list_head; 193 194 u64 live_lrs; 195 196 /* 197 * Members below are used with GICv3 emulation only and represent 198 * parts of the redistributor. 199 */ 200 struct vgic_io_device rd_iodev; 201 struct vgic_io_device sgi_iodev; 202 }; 203 204 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); 205 void kvm_vgic_early_init(struct kvm *kvm); 206 int kvm_vgic_create(struct kvm *kvm, u32 type); 207 void kvm_vgic_destroy(struct kvm *kvm); 208 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu); 209 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 210 int kvm_vgic_map_resources(struct kvm *kvm); 211 int kvm_vgic_hyp_init(void); 212 213 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid, 214 bool level); 215 int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid, 216 bool level); 217 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq); 218 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq); 219 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq); 220 221 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 222 223 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 224 #define vgic_initialized(k) ((k)->arch.vgic.initialized) 225 #define vgic_ready(k) ((k)->arch.vgic.ready) 226 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ 227 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) 228 229 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu); 230 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 231 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 232 233 #ifdef CONFIG_KVM_ARM_VGIC_V3 234 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); 235 #else 236 static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg) 237 { 238 } 239 #endif 240 241 /** 242 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW 243 * 244 * The host's GIC naturally limits the maximum amount of VCPUs a guest 245 * can use. 246 */ 247 static inline int kvm_vgic_get_max_vcpus(void) 248 { 249 return kvm_vgic_global_state.max_gic_vcpus; 250 } 251 252 #endif /* __KVM_ARM_VGIC_H */ 253