1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 19 #ifndef __ASM_ARM_KVM_VGIC_H 20 #define __ASM_ARM_KVM_VGIC_H 21 22 #include <linux/kernel.h> 23 #include <linux/kvm.h> 24 #include <linux/irqreturn.h> 25 #include <linux/spinlock.h> 26 #include <linux/types.h> 27 #include <kvm/iodev.h> 28 29 #define VGIC_NR_IRQS_LEGACY 256 30 #define VGIC_NR_SGIS 16 31 #define VGIC_NR_PPIS 16 32 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 33 34 #define VGIC_V2_MAX_LRS (1 << 6) 35 #define VGIC_V3_MAX_LRS 16 36 #define VGIC_MAX_IRQS 1024 37 #define VGIC_V2_MAX_CPUS 8 38 39 /* Sanity checks... */ 40 #if (KVM_MAX_VCPUS > 255) 41 #error Too many KVM VCPUs, the VGIC only supports up to 255 VCPUs for now 42 #endif 43 44 #if (VGIC_NR_IRQS_LEGACY & 31) 45 #error "VGIC_NR_IRQS must be a multiple of 32" 46 #endif 47 48 #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS) 49 #error "VGIC_NR_IRQS must be <= 1024" 50 #endif 51 52 /* 53 * The GIC distributor registers describing interrupts have two parts: 54 * - 32 per-CPU interrupts (SGI + PPI) 55 * - a bunch of shared interrupts (SPI) 56 */ 57 struct vgic_bitmap { 58 /* 59 * - One UL per VCPU for private interrupts (assumes UL is at 60 * least 32 bits) 61 * - As many UL as necessary for shared interrupts. 62 * 63 * The private interrupts are accessed via the "private" 64 * field, one UL per vcpu (the state for vcpu n is in 65 * private[n]). The shared interrupts are accessed via the 66 * "shared" pointer (IRQn state is at bit n-32 in the bitmap). 67 */ 68 unsigned long *private; 69 unsigned long *shared; 70 }; 71 72 struct vgic_bytemap { 73 /* 74 * - 8 u32 per VCPU for private interrupts 75 * - As many u32 as necessary for shared interrupts. 76 * 77 * The private interrupts are accessed via the "private" 78 * field, (the state for vcpu n is in private[n*8] to 79 * private[n*8 + 7]). The shared interrupts are accessed via 80 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the 81 * shared[(n-32)/4] word). 82 */ 83 u32 *private; 84 u32 *shared; 85 }; 86 87 struct kvm_vcpu; 88 89 enum vgic_type { 90 VGIC_V2, /* Good ol' GICv2 */ 91 VGIC_V3, /* New fancy GICv3 */ 92 }; 93 94 #define LR_STATE_PENDING (1 << 0) 95 #define LR_STATE_ACTIVE (1 << 1) 96 #define LR_STATE_MASK (3 << 0) 97 #define LR_EOI_INT (1 << 2) 98 #define LR_HW (1 << 3) 99 100 struct vgic_lr { 101 unsigned irq:10; 102 union { 103 unsigned hwirq:10; 104 unsigned source:3; 105 }; 106 unsigned state:4; 107 }; 108 109 struct vgic_vmcr { 110 u32 ctlr; 111 u32 abpr; 112 u32 bpr; 113 u32 pmr; 114 }; 115 116 struct vgic_ops { 117 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int); 118 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr); 119 void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr); 120 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu); 121 u64 (*get_eisr)(const struct kvm_vcpu *vcpu); 122 void (*clear_eisr)(struct kvm_vcpu *vcpu); 123 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu); 124 void (*enable_underflow)(struct kvm_vcpu *vcpu); 125 void (*disable_underflow)(struct kvm_vcpu *vcpu); 126 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 127 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 128 void (*enable)(struct kvm_vcpu *vcpu); 129 }; 130 131 struct vgic_params { 132 /* vgic type */ 133 enum vgic_type type; 134 /* Physical address of vgic virtual cpu interface */ 135 phys_addr_t vcpu_base; 136 /* Number of list registers */ 137 u32 nr_lr; 138 /* Interrupt number */ 139 unsigned int maint_irq; 140 /* Virtual control interface base address */ 141 void __iomem *vctrl_base; 142 int max_gic_vcpus; 143 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 144 bool can_emulate_gicv2; 145 }; 146 147 struct vgic_vm_ops { 148 bool (*queue_sgi)(struct kvm_vcpu *, int irq); 149 void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source); 150 int (*init_model)(struct kvm *); 151 int (*map_resources)(struct kvm *, const struct vgic_params *); 152 }; 153 154 struct vgic_io_device { 155 gpa_t addr; 156 int len; 157 const struct vgic_io_range *reg_ranges; 158 struct kvm_vcpu *redist_vcpu; 159 struct kvm_io_device dev; 160 }; 161 162 struct irq_phys_map { 163 u32 virt_irq; 164 u32 phys_irq; 165 u32 irq; 166 bool active; 167 }; 168 169 struct irq_phys_map_entry { 170 struct list_head entry; 171 struct rcu_head rcu; 172 struct irq_phys_map map; 173 }; 174 175 struct vgic_dist { 176 spinlock_t lock; 177 bool in_kernel; 178 bool ready; 179 180 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 181 u32 vgic_model; 182 183 int nr_cpus; 184 int nr_irqs; 185 186 /* Virtual control interface mapping */ 187 void __iomem *vctrl_base; 188 189 /* Distributor and vcpu interface mapping in the guest */ 190 phys_addr_t vgic_dist_base; 191 /* GICv2 and GICv3 use different mapped register blocks */ 192 union { 193 phys_addr_t vgic_cpu_base; 194 phys_addr_t vgic_redist_base; 195 }; 196 197 /* Distributor enabled */ 198 u32 enabled; 199 200 /* Interrupt enabled (one bit per IRQ) */ 201 struct vgic_bitmap irq_enabled; 202 203 /* Level-triggered interrupt external input is asserted */ 204 struct vgic_bitmap irq_level; 205 206 /* 207 * Interrupt state is pending on the distributor 208 */ 209 struct vgic_bitmap irq_pending; 210 211 /* 212 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered 213 * interrupts. Essentially holds the state of the flip-flop in 214 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b. 215 * Once set, it is only cleared for level-triggered interrupts on 216 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn. 217 */ 218 struct vgic_bitmap irq_soft_pend; 219 220 /* Level-triggered interrupt queued on VCPU interface */ 221 struct vgic_bitmap irq_queued; 222 223 /* Interrupt was active when unqueue from VCPU interface */ 224 struct vgic_bitmap irq_active; 225 226 /* Interrupt priority. Not used yet. */ 227 struct vgic_bytemap irq_priority; 228 229 /* Level/edge triggered */ 230 struct vgic_bitmap irq_cfg; 231 232 /* 233 * Source CPU per SGI and target CPU: 234 * 235 * Each byte represent a SGI observable on a VCPU, each bit of 236 * this byte indicating if the corresponding VCPU has 237 * generated this interrupt. This is a GICv2 feature only. 238 * 239 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are 240 * the SGIs observable on VCPUn. 241 */ 242 u8 *irq_sgi_sources; 243 244 /* 245 * Target CPU for each SPI: 246 * 247 * Array of available SPI, each byte indicating the target 248 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32]. 249 */ 250 u8 *irq_spi_cpu; 251 252 /* 253 * Reverse lookup of irq_spi_cpu for faster compute pending: 254 * 255 * Array of bitmaps, one per VCPU, describing if IRQn is 256 * routed to a particular VCPU. 257 */ 258 struct vgic_bitmap *irq_spi_target; 259 260 /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */ 261 u32 *irq_spi_mpidr; 262 263 /* Bitmap indicating which CPU has something pending */ 264 unsigned long *irq_pending_on_cpu; 265 266 /* Bitmap indicating which CPU has active IRQs */ 267 unsigned long *irq_active_on_cpu; 268 269 struct vgic_vm_ops vm_ops; 270 struct vgic_io_device dist_iodev; 271 struct vgic_io_device *redist_iodevs; 272 273 /* Virtual irq to hwirq mapping */ 274 spinlock_t irq_phys_map_lock; 275 struct list_head irq_phys_map_list; 276 }; 277 278 struct vgic_v2_cpu_if { 279 u32 vgic_hcr; 280 u32 vgic_vmcr; 281 u32 vgic_misr; /* Saved only */ 282 u64 vgic_eisr; /* Saved only */ 283 u64 vgic_elrsr; /* Saved only */ 284 u32 vgic_apr; 285 u32 vgic_lr[VGIC_V2_MAX_LRS]; 286 }; 287 288 struct vgic_v3_cpu_if { 289 #ifdef CONFIG_ARM_GIC_V3 290 u32 vgic_hcr; 291 u32 vgic_vmcr; 292 u32 vgic_sre; /* Restored only, change ignored */ 293 u32 vgic_misr; /* Saved only */ 294 u32 vgic_eisr; /* Saved only */ 295 u32 vgic_elrsr; /* Saved only */ 296 u32 vgic_ap0r[4]; 297 u32 vgic_ap1r[4]; 298 u64 vgic_lr[VGIC_V3_MAX_LRS]; 299 #endif 300 }; 301 302 struct vgic_cpu { 303 /* per IRQ to LR mapping */ 304 u8 *vgic_irq_lr_map; 305 306 /* Pending/active/both interrupts on this VCPU */ 307 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS); 308 DECLARE_BITMAP( active_percpu, VGIC_NR_PRIVATE_IRQS); 309 DECLARE_BITMAP( pend_act_percpu, VGIC_NR_PRIVATE_IRQS); 310 311 /* Pending/active/both shared interrupts, dynamically sized */ 312 unsigned long *pending_shared; 313 unsigned long *active_shared; 314 unsigned long *pend_act_shared; 315 316 /* Bitmap of used/free list registers */ 317 DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS); 318 319 /* Number of list registers on this CPU */ 320 int nr_lr; 321 322 /* CPU vif control registers for world switch */ 323 union { 324 struct vgic_v2_cpu_if vgic_v2; 325 struct vgic_v3_cpu_if vgic_v3; 326 }; 327 328 /* Protected by the distributor's irq_phys_map_lock */ 329 struct list_head irq_phys_map_list; 330 }; 331 332 #define LR_EMPTY 0xff 333 334 #define INT_STATUS_EOI (1 << 0) 335 #define INT_STATUS_UNDERFLOW (1 << 1) 336 337 struct kvm; 338 struct kvm_vcpu; 339 340 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); 341 int kvm_vgic_hyp_init(void); 342 int kvm_vgic_map_resources(struct kvm *kvm); 343 int kvm_vgic_get_max_vcpus(void); 344 void kvm_vgic_early_init(struct kvm *kvm); 345 int kvm_vgic_create(struct kvm *kvm, u32 type); 346 void kvm_vgic_destroy(struct kvm *kvm); 347 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu); 348 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 349 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 350 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 351 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, 352 bool level); 353 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); 354 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 355 int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu); 356 struct irq_phys_map *kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, 357 int virt_irq, int irq); 358 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, struct irq_phys_map *map); 359 bool kvm_vgic_get_phys_irq_active(struct irq_phys_map *map); 360 void kvm_vgic_set_phys_irq_active(struct irq_phys_map *map, bool active); 361 362 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 363 #define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus)) 364 #define vgic_ready(k) ((k)->arch.vgic.ready) 365 366 int vgic_v2_probe(struct device_node *vgic_node, 367 const struct vgic_ops **ops, 368 const struct vgic_params **params); 369 #ifdef CONFIG_ARM_GIC_V3 370 int vgic_v3_probe(struct device_node *vgic_node, 371 const struct vgic_ops **ops, 372 const struct vgic_params **params); 373 #else 374 static inline int vgic_v3_probe(struct device_node *vgic_node, 375 const struct vgic_ops **ops, 376 const struct vgic_params **params) 377 { 378 return -ENODEV; 379 } 380 #endif 381 382 #endif 383