1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 19 #ifndef __ASM_ARM_KVM_VGIC_H 20 #define __ASM_ARM_KVM_VGIC_H 21 22 #include <linux/kernel.h> 23 #include <linux/kvm.h> 24 #include <linux/irqreturn.h> 25 #include <linux/spinlock.h> 26 #include <linux/types.h> 27 28 #define VGIC_NR_IRQS 256 29 #define VGIC_NR_SGIS 16 30 #define VGIC_NR_PPIS 16 31 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 32 #define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS) 33 #define VGIC_MAX_CPUS KVM_MAX_VCPUS 34 35 #define VGIC_V2_MAX_LRS (1 << 6) 36 #define VGIC_V3_MAX_LRS 16 37 38 /* Sanity checks... */ 39 #if (VGIC_MAX_CPUS > 8) 40 #error Invalid number of CPU interfaces 41 #endif 42 43 #if (VGIC_NR_IRQS & 31) 44 #error "VGIC_NR_IRQS must be a multiple of 32" 45 #endif 46 47 #if (VGIC_NR_IRQS > 1024) 48 #error "VGIC_NR_IRQS must be <= 1024" 49 #endif 50 51 /* 52 * The GIC distributor registers describing interrupts have two parts: 53 * - 32 per-CPU interrupts (SGI + PPI) 54 * - a bunch of shared interrupts (SPI) 55 */ 56 struct vgic_bitmap { 57 union { 58 u32 reg[VGIC_NR_PRIVATE_IRQS / 32]; 59 DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS); 60 } percpu[VGIC_MAX_CPUS]; 61 union { 62 u32 reg[VGIC_NR_SHARED_IRQS / 32]; 63 DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS); 64 } shared; 65 }; 66 67 struct vgic_bytemap { 68 u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4]; 69 u32 shared[VGIC_NR_SHARED_IRQS / 4]; 70 }; 71 72 struct kvm_vcpu; 73 74 enum vgic_type { 75 VGIC_V2, /* Good ol' GICv2 */ 76 VGIC_V3, /* New fancy GICv3 */ 77 }; 78 79 #define LR_STATE_PENDING (1 << 0) 80 #define LR_STATE_ACTIVE (1 << 1) 81 #define LR_STATE_MASK (3 << 0) 82 #define LR_EOI_INT (1 << 2) 83 84 struct vgic_lr { 85 u16 irq; 86 u8 source; 87 u8 state; 88 }; 89 90 struct vgic_vmcr { 91 u32 ctlr; 92 u32 abpr; 93 u32 bpr; 94 u32 pmr; 95 }; 96 97 struct vgic_ops { 98 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int); 99 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr); 100 void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr); 101 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu); 102 u64 (*get_eisr)(const struct kvm_vcpu *vcpu); 103 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu); 104 void (*enable_underflow)(struct kvm_vcpu *vcpu); 105 void (*disable_underflow)(struct kvm_vcpu *vcpu); 106 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 107 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 108 void (*enable)(struct kvm_vcpu *vcpu); 109 }; 110 111 struct vgic_params { 112 /* vgic type */ 113 enum vgic_type type; 114 /* Physical address of vgic virtual cpu interface */ 115 phys_addr_t vcpu_base; 116 /* Number of list registers */ 117 u32 nr_lr; 118 /* Interrupt number */ 119 unsigned int maint_irq; 120 /* Virtual control interface base address */ 121 void __iomem *vctrl_base; 122 }; 123 124 struct vgic_dist { 125 #ifdef CONFIG_KVM_ARM_VGIC 126 spinlock_t lock; 127 bool in_kernel; 128 bool ready; 129 130 /* Virtual control interface mapping */ 131 void __iomem *vctrl_base; 132 133 /* Distributor and vcpu interface mapping in the guest */ 134 phys_addr_t vgic_dist_base; 135 phys_addr_t vgic_cpu_base; 136 137 /* Distributor enabled */ 138 u32 enabled; 139 140 /* Interrupt enabled (one bit per IRQ) */ 141 struct vgic_bitmap irq_enabled; 142 143 /* Interrupt 'pin' level */ 144 struct vgic_bitmap irq_state; 145 146 /* Level-triggered interrupt in progress */ 147 struct vgic_bitmap irq_active; 148 149 /* Interrupt priority. Not used yet. */ 150 struct vgic_bytemap irq_priority; 151 152 /* Level/edge triggered */ 153 struct vgic_bitmap irq_cfg; 154 155 /* Source CPU per SGI and target CPU */ 156 u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS]; 157 158 /* Target CPU for each IRQ */ 159 u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS]; 160 struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS]; 161 162 /* Bitmap indicating which CPU has something pending */ 163 unsigned long irq_pending_on_cpu; 164 #endif 165 }; 166 167 struct vgic_v2_cpu_if { 168 u32 vgic_hcr; 169 u32 vgic_vmcr; 170 u32 vgic_misr; /* Saved only */ 171 u32 vgic_eisr[2]; /* Saved only */ 172 u32 vgic_elrsr[2]; /* Saved only */ 173 u32 vgic_apr; 174 u32 vgic_lr[VGIC_V2_MAX_LRS]; 175 }; 176 177 struct vgic_v3_cpu_if { 178 #ifdef CONFIG_ARM_GIC_V3 179 u32 vgic_hcr; 180 u32 vgic_vmcr; 181 u32 vgic_misr; /* Saved only */ 182 u32 vgic_eisr; /* Saved only */ 183 u32 vgic_elrsr; /* Saved only */ 184 u32 vgic_ap0r[4]; 185 u32 vgic_ap1r[4]; 186 u64 vgic_lr[VGIC_V3_MAX_LRS]; 187 #endif 188 }; 189 190 struct vgic_cpu { 191 #ifdef CONFIG_KVM_ARM_VGIC 192 /* per IRQ to LR mapping */ 193 u8 vgic_irq_lr_map[VGIC_NR_IRQS]; 194 195 /* Pending interrupts on this VCPU */ 196 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS); 197 DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS); 198 199 /* Bitmap of used/free list registers */ 200 DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS); 201 202 /* Number of list registers on this CPU */ 203 int nr_lr; 204 205 /* CPU vif control registers for world switch */ 206 union { 207 struct vgic_v2_cpu_if vgic_v2; 208 struct vgic_v3_cpu_if vgic_v3; 209 }; 210 #endif 211 }; 212 213 #define LR_EMPTY 0xff 214 215 #define INT_STATUS_EOI (1 << 0) 216 #define INT_STATUS_UNDERFLOW (1 << 1) 217 218 struct kvm; 219 struct kvm_vcpu; 220 struct kvm_run; 221 struct kvm_exit_mmio; 222 223 #ifdef CONFIG_KVM_ARM_VGIC 224 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); 225 int kvm_vgic_hyp_init(void); 226 int kvm_vgic_init(struct kvm *kvm); 227 int kvm_vgic_create(struct kvm *kvm); 228 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); 229 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 230 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 231 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, 232 bool level); 233 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 234 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, 235 struct kvm_exit_mmio *mmio); 236 237 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 238 #define vgic_initialized(k) ((k)->arch.vgic.ready) 239 240 int vgic_v2_probe(struct device_node *vgic_node, 241 const struct vgic_ops **ops, 242 const struct vgic_params **params); 243 #ifdef CONFIG_ARM_GIC_V3 244 int vgic_v3_probe(struct device_node *vgic_node, 245 const struct vgic_ops **ops, 246 const struct vgic_params **params); 247 #else 248 static inline int vgic_v3_probe(struct device_node *vgic_node, 249 const struct vgic_ops **ops, 250 const struct vgic_params **params) 251 { 252 return -ENODEV; 253 } 254 #endif 255 256 #else 257 static inline int kvm_vgic_hyp_init(void) 258 { 259 return 0; 260 } 261 262 static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr) 263 { 264 return 0; 265 } 266 267 static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) 268 { 269 return -ENXIO; 270 } 271 272 static inline int kvm_vgic_init(struct kvm *kvm) 273 { 274 return 0; 275 } 276 277 static inline int kvm_vgic_create(struct kvm *kvm) 278 { 279 return 0; 280 } 281 282 static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) 283 { 284 return 0; 285 } 286 287 static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {} 288 static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {} 289 290 static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, 291 unsigned int irq_num, bool level) 292 { 293 return 0; 294 } 295 296 static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) 297 { 298 return 0; 299 } 300 301 static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, 302 struct kvm_exit_mmio *mmio) 303 { 304 return false; 305 } 306 307 static inline int irqchip_in_kernel(struct kvm *kvm) 308 { 309 return 0; 310 } 311 312 static inline bool vgic_initialized(struct kvm *kvm) 313 { 314 return true; 315 } 316 #endif 317 318 #endif 319