1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 19 #ifndef __ASM_ARM_KVM_VGIC_H 20 #define __ASM_ARM_KVM_VGIC_H 21 22 #include <linux/kernel.h> 23 #include <linux/kvm.h> 24 #include <linux/irqreturn.h> 25 #include <linux/spinlock.h> 26 #include <linux/types.h> 27 #include <kvm/iodev.h> 28 29 #define VGIC_NR_IRQS_LEGACY 256 30 #define VGIC_NR_SGIS 16 31 #define VGIC_NR_PPIS 16 32 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 33 34 #define VGIC_V2_MAX_LRS (1 << 6) 35 #define VGIC_V3_MAX_LRS 16 36 #define VGIC_MAX_IRQS 1024 37 #define VGIC_V2_MAX_CPUS 8 38 39 /* Sanity checks... */ 40 #if (KVM_MAX_VCPUS > 255) 41 #error Too many KVM VCPUs, the VGIC only supports up to 255 VCPUs for now 42 #endif 43 44 #if (VGIC_NR_IRQS_LEGACY & 31) 45 #error "VGIC_NR_IRQS must be a multiple of 32" 46 #endif 47 48 #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS) 49 #error "VGIC_NR_IRQS must be <= 1024" 50 #endif 51 52 /* 53 * The GIC distributor registers describing interrupts have two parts: 54 * - 32 per-CPU interrupts (SGI + PPI) 55 * - a bunch of shared interrupts (SPI) 56 */ 57 struct vgic_bitmap { 58 /* 59 * - One UL per VCPU for private interrupts (assumes UL is at 60 * least 32 bits) 61 * - As many UL as necessary for shared interrupts. 62 * 63 * The private interrupts are accessed via the "private" 64 * field, one UL per vcpu (the state for vcpu n is in 65 * private[n]). The shared interrupts are accessed via the 66 * "shared" pointer (IRQn state is at bit n-32 in the bitmap). 67 */ 68 unsigned long *private; 69 unsigned long *shared; 70 }; 71 72 struct vgic_bytemap { 73 /* 74 * - 8 u32 per VCPU for private interrupts 75 * - As many u32 as necessary for shared interrupts. 76 * 77 * The private interrupts are accessed via the "private" 78 * field, (the state for vcpu n is in private[n*8] to 79 * private[n*8 + 7]). The shared interrupts are accessed via 80 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the 81 * shared[(n-32)/4] word). 82 */ 83 u32 *private; 84 u32 *shared; 85 }; 86 87 struct kvm_vcpu; 88 89 enum vgic_type { 90 VGIC_V2, /* Good ol' GICv2 */ 91 VGIC_V3, /* New fancy GICv3 */ 92 }; 93 94 #define LR_STATE_PENDING (1 << 0) 95 #define LR_STATE_ACTIVE (1 << 1) 96 #define LR_STATE_MASK (3 << 0) 97 #define LR_EOI_INT (1 << 2) 98 #define LR_HW (1 << 3) 99 100 struct vgic_lr { 101 unsigned irq:10; 102 union { 103 unsigned hwirq:10; 104 unsigned source:3; 105 }; 106 unsigned state:4; 107 }; 108 109 struct vgic_vmcr { 110 u32 ctlr; 111 u32 abpr; 112 u32 bpr; 113 u32 pmr; 114 }; 115 116 struct vgic_ops { 117 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int); 118 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr); 119 void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr); 120 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu); 121 u64 (*get_eisr)(const struct kvm_vcpu *vcpu); 122 void (*clear_eisr)(struct kvm_vcpu *vcpu); 123 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu); 124 void (*enable_underflow)(struct kvm_vcpu *vcpu); 125 void (*disable_underflow)(struct kvm_vcpu *vcpu); 126 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 127 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 128 void (*enable)(struct kvm_vcpu *vcpu); 129 }; 130 131 struct vgic_params { 132 /* vgic type */ 133 enum vgic_type type; 134 /* Physical address of vgic virtual cpu interface */ 135 phys_addr_t vcpu_base; 136 /* Number of list registers */ 137 u32 nr_lr; 138 /* Interrupt number */ 139 unsigned int maint_irq; 140 /* Virtual control interface base address */ 141 void __iomem *vctrl_base; 142 int max_gic_vcpus; 143 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 144 bool can_emulate_gicv2; 145 }; 146 147 struct vgic_vm_ops { 148 bool (*queue_sgi)(struct kvm_vcpu *, int irq); 149 void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source); 150 int (*init_model)(struct kvm *); 151 int (*map_resources)(struct kvm *, const struct vgic_params *); 152 }; 153 154 struct vgic_io_device { 155 gpa_t addr; 156 int len; 157 const struct vgic_io_range *reg_ranges; 158 struct kvm_vcpu *redist_vcpu; 159 struct kvm_io_device dev; 160 }; 161 162 struct vgic_dist { 163 spinlock_t lock; 164 bool in_kernel; 165 bool ready; 166 167 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 168 u32 vgic_model; 169 170 int nr_cpus; 171 int nr_irqs; 172 173 /* Virtual control interface mapping */ 174 void __iomem *vctrl_base; 175 176 /* Distributor and vcpu interface mapping in the guest */ 177 phys_addr_t vgic_dist_base; 178 /* GICv2 and GICv3 use different mapped register blocks */ 179 union { 180 phys_addr_t vgic_cpu_base; 181 phys_addr_t vgic_redist_base; 182 }; 183 184 /* Distributor enabled */ 185 u32 enabled; 186 187 /* Interrupt enabled (one bit per IRQ) */ 188 struct vgic_bitmap irq_enabled; 189 190 /* Level-triggered interrupt external input is asserted */ 191 struct vgic_bitmap irq_level; 192 193 /* 194 * Interrupt state is pending on the distributor 195 */ 196 struct vgic_bitmap irq_pending; 197 198 /* 199 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered 200 * interrupts. Essentially holds the state of the flip-flop in 201 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b. 202 * Once set, it is only cleared for level-triggered interrupts on 203 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn. 204 */ 205 struct vgic_bitmap irq_soft_pend; 206 207 /* Level-triggered interrupt queued on VCPU interface */ 208 struct vgic_bitmap irq_queued; 209 210 /* Interrupt was active when unqueue from VCPU interface */ 211 struct vgic_bitmap irq_active; 212 213 /* Interrupt priority. Not used yet. */ 214 struct vgic_bytemap irq_priority; 215 216 /* Level/edge triggered */ 217 struct vgic_bitmap irq_cfg; 218 219 /* 220 * Source CPU per SGI and target CPU: 221 * 222 * Each byte represent a SGI observable on a VCPU, each bit of 223 * this byte indicating if the corresponding VCPU has 224 * generated this interrupt. This is a GICv2 feature only. 225 * 226 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are 227 * the SGIs observable on VCPUn. 228 */ 229 u8 *irq_sgi_sources; 230 231 /* 232 * Target CPU for each SPI: 233 * 234 * Array of available SPI, each byte indicating the target 235 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32]. 236 */ 237 u8 *irq_spi_cpu; 238 239 /* 240 * Reverse lookup of irq_spi_cpu for faster compute pending: 241 * 242 * Array of bitmaps, one per VCPU, describing if IRQn is 243 * routed to a particular VCPU. 244 */ 245 struct vgic_bitmap *irq_spi_target; 246 247 /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */ 248 u32 *irq_spi_mpidr; 249 250 /* Bitmap indicating which CPU has something pending */ 251 unsigned long *irq_pending_on_cpu; 252 253 /* Bitmap indicating which CPU has active IRQs */ 254 unsigned long *irq_active_on_cpu; 255 256 struct vgic_vm_ops vm_ops; 257 struct vgic_io_device dist_iodev; 258 struct vgic_io_device *redist_iodevs; 259 }; 260 261 struct vgic_v2_cpu_if { 262 u32 vgic_hcr; 263 u32 vgic_vmcr; 264 u32 vgic_misr; /* Saved only */ 265 u64 vgic_eisr; /* Saved only */ 266 u64 vgic_elrsr; /* Saved only */ 267 u32 vgic_apr; 268 u32 vgic_lr[VGIC_V2_MAX_LRS]; 269 }; 270 271 struct vgic_v3_cpu_if { 272 #ifdef CONFIG_ARM_GIC_V3 273 u32 vgic_hcr; 274 u32 vgic_vmcr; 275 u32 vgic_sre; /* Restored only, change ignored */ 276 u32 vgic_misr; /* Saved only */ 277 u32 vgic_eisr; /* Saved only */ 278 u32 vgic_elrsr; /* Saved only */ 279 u32 vgic_ap0r[4]; 280 u32 vgic_ap1r[4]; 281 u64 vgic_lr[VGIC_V3_MAX_LRS]; 282 #endif 283 }; 284 285 struct vgic_cpu { 286 /* per IRQ to LR mapping */ 287 u8 *vgic_irq_lr_map; 288 289 /* Pending/active/both interrupts on this VCPU */ 290 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS); 291 DECLARE_BITMAP( active_percpu, VGIC_NR_PRIVATE_IRQS); 292 DECLARE_BITMAP( pend_act_percpu, VGIC_NR_PRIVATE_IRQS); 293 294 /* Pending/active/both shared interrupts, dynamically sized */ 295 unsigned long *pending_shared; 296 unsigned long *active_shared; 297 unsigned long *pend_act_shared; 298 299 /* Bitmap of used/free list registers */ 300 DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS); 301 302 /* Number of list registers on this CPU */ 303 int nr_lr; 304 305 /* CPU vif control registers for world switch */ 306 union { 307 struct vgic_v2_cpu_if vgic_v2; 308 struct vgic_v3_cpu_if vgic_v3; 309 }; 310 }; 311 312 #define LR_EMPTY 0xff 313 314 #define INT_STATUS_EOI (1 << 0) 315 #define INT_STATUS_UNDERFLOW (1 << 1) 316 317 struct kvm; 318 struct kvm_vcpu; 319 320 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); 321 int kvm_vgic_hyp_init(void); 322 int kvm_vgic_map_resources(struct kvm *kvm); 323 int kvm_vgic_get_max_vcpus(void); 324 int kvm_vgic_create(struct kvm *kvm, u32 type); 325 void kvm_vgic_destroy(struct kvm *kvm); 326 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 327 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 328 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 329 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, 330 bool level); 331 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); 332 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 333 int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu); 334 335 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 336 #define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus)) 337 #define vgic_ready(k) ((k)->arch.vgic.ready) 338 339 int vgic_v2_probe(struct device_node *vgic_node, 340 const struct vgic_ops **ops, 341 const struct vgic_params **params); 342 #ifdef CONFIG_ARM_GIC_V3 343 int vgic_v3_probe(struct device_node *vgic_node, 344 const struct vgic_ops **ops, 345 const struct vgic_params **params); 346 #else 347 static inline int vgic_v3_probe(struct device_node *vgic_node, 348 const struct vgic_ops **ops, 349 const struct vgic_params **params) 350 { 351 return -ENODEV; 352 } 353 #endif 354 355 #endif 356