1 /* 2 * Copyright (C) 2015, 2016 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __KVM_ARM_VGIC_H 17 #define __KVM_ARM_VGIC_H 18 19 #include <linux/kernel.h> 20 #include <linux/kvm.h> 21 #include <linux/irqreturn.h> 22 #include <linux/spinlock.h> 23 #include <linux/types.h> 24 #include <kvm/iodev.h> 25 #include <linux/list.h> 26 27 #define VGIC_V3_MAX_CPUS 255 28 #define VGIC_V2_MAX_CPUS 8 29 #define VGIC_NR_IRQS_LEGACY 256 30 #define VGIC_NR_SGIS 16 31 #define VGIC_NR_PPIS 16 32 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 33 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) 34 #define VGIC_MAX_SPI 1019 35 #define VGIC_MAX_RESERVED 1023 36 #define VGIC_MIN_LPI 8192 37 #define KVM_IRQCHIP_NUM_PINS (1020 - 32) 38 39 enum vgic_type { 40 VGIC_V2, /* Good ol' GICv2 */ 41 VGIC_V3, /* New fancy GICv3 */ 42 }; 43 44 /* same for all guests, as depending only on the _host's_ GIC model */ 45 struct vgic_global { 46 /* type of the host GIC */ 47 enum vgic_type type; 48 49 /* Physical address of vgic virtual cpu interface */ 50 phys_addr_t vcpu_base; 51 52 /* virtual control interface mapping */ 53 void __iomem *vctrl_base; 54 55 /* Number of implemented list registers */ 56 int nr_lr; 57 58 /* Maintenance IRQ number */ 59 unsigned int maint_irq; 60 61 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */ 62 int max_gic_vcpus; 63 64 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 65 bool can_emulate_gicv2; 66 }; 67 68 extern struct vgic_global kvm_vgic_global_state; 69 70 #define VGIC_V2_MAX_LRS (1 << 6) 71 #define VGIC_V3_MAX_LRS 16 72 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) 73 74 enum vgic_irq_config { 75 VGIC_CONFIG_EDGE = 0, 76 VGIC_CONFIG_LEVEL 77 }; 78 79 struct vgic_irq { 80 spinlock_t irq_lock; /* Protects the content of the struct */ 81 struct list_head lpi_list; /* Used to link all LPIs together */ 82 struct list_head ap_list; 83 84 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU 85 * SPIs and LPIs: The VCPU whose ap_list 86 * this is queued on. 87 */ 88 89 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should 90 * be sent to, as a result of the 91 * targets reg (v2) or the 92 * affinity reg (v3). 93 */ 94 95 u32 intid; /* Guest visible INTID */ 96 bool pending; 97 bool line_level; /* Level only */ 98 bool soft_pending; /* Level only */ 99 bool active; /* not used for LPIs */ 100 bool enabled; 101 bool hw; /* Tied to HW IRQ */ 102 struct kref refcount; /* Used for LPIs */ 103 u32 hwintid; /* HW INTID number */ 104 union { 105 u8 targets; /* GICv2 target VCPUs mask */ 106 u32 mpidr; /* GICv3 target VCPU */ 107 }; 108 u8 source; /* GICv2 SGIs only */ 109 u8 priority; 110 enum vgic_irq_config config; /* Level or edge */ 111 }; 112 113 struct vgic_register_region; 114 struct vgic_its; 115 116 enum iodev_type { 117 IODEV_CPUIF, 118 IODEV_DIST, 119 IODEV_REDIST, 120 IODEV_ITS 121 }; 122 123 struct vgic_io_device { 124 gpa_t base_addr; 125 union { 126 struct kvm_vcpu *redist_vcpu; 127 struct vgic_its *its; 128 }; 129 const struct vgic_register_region *regions; 130 enum iodev_type iodev_type; 131 int nr_regions; 132 struct kvm_io_device dev; 133 }; 134 135 struct vgic_its { 136 /* The base address of the ITS control register frame */ 137 gpa_t vgic_its_base; 138 139 bool enabled; 140 bool initialized; 141 struct vgic_io_device iodev; 142 struct kvm_device *dev; 143 144 /* These registers correspond to GITS_BASER{0,1} */ 145 u64 baser_device_table; 146 u64 baser_coll_table; 147 148 /* Protects the command queue */ 149 struct mutex cmd_lock; 150 u64 cbaser; 151 u32 creadr; 152 u32 cwriter; 153 154 /* Protects the device and collection lists */ 155 struct mutex its_lock; 156 struct list_head device_list; 157 struct list_head collection_list; 158 }; 159 160 struct vgic_dist { 161 bool in_kernel; 162 bool ready; 163 bool initialized; 164 165 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 166 u32 vgic_model; 167 168 /* Do injected MSIs require an additional device ID? */ 169 bool msis_require_devid; 170 171 int nr_spis; 172 173 /* TODO: Consider moving to global state */ 174 /* Virtual control interface mapping */ 175 void __iomem *vctrl_base; 176 177 /* base addresses in guest physical address space: */ 178 gpa_t vgic_dist_base; /* distributor */ 179 union { 180 /* either a GICv2 CPU interface */ 181 gpa_t vgic_cpu_base; 182 /* or a number of GICv3 redistributor regions */ 183 gpa_t vgic_redist_base; 184 }; 185 186 /* distributor enabled */ 187 bool enabled; 188 189 struct vgic_irq *spis; 190 191 struct vgic_io_device dist_iodev; 192 193 bool has_its; 194 195 /* 196 * Contains the attributes and gpa of the LPI configuration table. 197 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share 198 * one address across all redistributors. 199 * GICv3 spec: 6.1.2 "LPI Configuration tables" 200 */ 201 u64 propbaser; 202 203 /* Protects the lpi_list and the count value below. */ 204 spinlock_t lpi_list_lock; 205 struct list_head lpi_list_head; 206 int lpi_list_count; 207 }; 208 209 struct vgic_v2_cpu_if { 210 u32 vgic_hcr; 211 u32 vgic_vmcr; 212 u32 vgic_misr; /* Saved only */ 213 u64 vgic_eisr; /* Saved only */ 214 u64 vgic_elrsr; /* Saved only */ 215 u32 vgic_apr; 216 u32 vgic_lr[VGIC_V2_MAX_LRS]; 217 }; 218 219 struct vgic_v3_cpu_if { 220 #ifdef CONFIG_KVM_ARM_VGIC_V3 221 u32 vgic_hcr; 222 u32 vgic_vmcr; 223 u32 vgic_sre; /* Restored only, change ignored */ 224 u32 vgic_misr; /* Saved only */ 225 u32 vgic_eisr; /* Saved only */ 226 u32 vgic_elrsr; /* Saved only */ 227 u32 vgic_ap0r[4]; 228 u32 vgic_ap1r[4]; 229 u64 vgic_lr[VGIC_V3_MAX_LRS]; 230 #endif 231 }; 232 233 struct vgic_cpu { 234 /* CPU vif control registers for world switch */ 235 union { 236 struct vgic_v2_cpu_if vgic_v2; 237 struct vgic_v3_cpu_if vgic_v3; 238 }; 239 240 unsigned int used_lrs; 241 struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; 242 243 spinlock_t ap_list_lock; /* Protects the ap_list */ 244 245 /* 246 * List of IRQs that this VCPU should consider because they are either 247 * Active or Pending (hence the name; AP list), or because they recently 248 * were one of the two and need to be migrated off this list to another 249 * VCPU. 250 */ 251 struct list_head ap_list_head; 252 253 u64 live_lrs; 254 255 /* 256 * Members below are used with GICv3 emulation only and represent 257 * parts of the redistributor. 258 */ 259 struct vgic_io_device rd_iodev; 260 struct vgic_io_device sgi_iodev; 261 262 /* Contains the attributes and gpa of the LPI pending tables. */ 263 u64 pendbaser; 264 265 bool lpis_enabled; 266 }; 267 268 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); 269 void kvm_vgic_early_init(struct kvm *kvm); 270 int kvm_vgic_create(struct kvm *kvm, u32 type); 271 void kvm_vgic_destroy(struct kvm *kvm); 272 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu); 273 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 274 int kvm_vgic_map_resources(struct kvm *kvm); 275 int kvm_vgic_hyp_init(void); 276 277 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid, 278 bool level); 279 int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid, 280 bool level); 281 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq); 282 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq); 283 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq); 284 285 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 286 287 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 288 #define vgic_initialized(k) ((k)->arch.vgic.initialized) 289 #define vgic_ready(k) ((k)->arch.vgic.ready) 290 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ 291 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) 292 293 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu); 294 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 295 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 296 297 #ifdef CONFIG_KVM_ARM_VGIC_V3 298 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); 299 #else 300 static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg) 301 { 302 } 303 #endif 304 305 /** 306 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW 307 * 308 * The host's GIC naturally limits the maximum amount of VCPUs a guest 309 * can use. 310 */ 311 static inline int kvm_vgic_get_max_vcpus(void) 312 { 313 return kvm_vgic_global_state.max_gic_vcpus; 314 } 315 316 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi); 317 318 /** 319 * kvm_vgic_setup_default_irq_routing: 320 * Setup a default flat gsi routing table mapping all SPIs 321 */ 322 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm); 323 324 #endif /* __KVM_ARM_VGIC_H */ 325