1d2a3b501SZev Weiss /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2d2a3b501SZev Weiss 3d2a3b501SZev Weiss #ifndef DT_BINDINGS_ASPEED_WDT_H 4d2a3b501SZev Weiss #define DT_BINDINGS_ASPEED_WDT_H 5d2a3b501SZev Weiss 6d2a3b501SZev Weiss #define AST2500_WDT_RESET_CPU (1 << 0) 7d2a3b501SZev Weiss #define AST2500_WDT_RESET_COPROC (1 << 1) 8d2a3b501SZev Weiss #define AST2500_WDT_RESET_SDRAM (1 << 2) 9d2a3b501SZev Weiss #define AST2500_WDT_RESET_AHB (1 << 3) 10d2a3b501SZev Weiss #define AST2500_WDT_RESET_I2C (1 << 4) 11d2a3b501SZev Weiss #define AST2500_WDT_RESET_MAC0 (1 << 5) 12d2a3b501SZev Weiss #define AST2500_WDT_RESET_MAC1 (1 << 6) 13d2a3b501SZev Weiss #define AST2500_WDT_RESET_GRAPHICS (1 << 7) 14d2a3b501SZev Weiss #define AST2500_WDT_RESET_USB2_HOST_HUB (1 << 8) 15d2a3b501SZev Weiss #define AST2500_WDT_RESET_USB_HOST (1 << 9) 16d2a3b501SZev Weiss #define AST2500_WDT_RESET_HID_EHCI (1 << 10) 17d2a3b501SZev Weiss #define AST2500_WDT_RESET_VIDEO (1 << 11) 18d2a3b501SZev Weiss #define AST2500_WDT_RESET_HAC (1 << 12) 19d2a3b501SZev Weiss #define AST2500_WDT_RESET_LPC (1 << 13) 20d2a3b501SZev Weiss #define AST2500_WDT_RESET_SDIO (1 << 14) 21d2a3b501SZev Weiss #define AST2500_WDT_RESET_MIC (1 << 15) 22d2a3b501SZev Weiss #define AST2500_WDT_RESET_CRT (1 << 16) 23d2a3b501SZev Weiss #define AST2500_WDT_RESET_PWM (1 << 17) 24d2a3b501SZev Weiss #define AST2500_WDT_RESET_PECI (1 << 18) 25d2a3b501SZev Weiss #define AST2500_WDT_RESET_JTAG (1 << 19) 26d2a3b501SZev Weiss #define AST2500_WDT_RESET_ADC (1 << 20) 27d2a3b501SZev Weiss #define AST2500_WDT_RESET_GPIO (1 << 21) 28d2a3b501SZev Weiss #define AST2500_WDT_RESET_MCTP (1 << 22) 29d2a3b501SZev Weiss #define AST2500_WDT_RESET_XDMA (1 << 23) 30d2a3b501SZev Weiss #define AST2500_WDT_RESET_SPI (1 << 24) 31d2a3b501SZev Weiss #define AST2500_WDT_RESET_SOC_MISC (1 << 25) 32d2a3b501SZev Weiss 33d2a3b501SZev Weiss #define AST2500_WDT_RESET_DEFAULT 0x023ffff3 34d2a3b501SZev Weiss 35d2a3b501SZev Weiss #define AST2600_WDT_RESET1_CPU (1 << 0) 36d2a3b501SZev Weiss #define AST2600_WDT_RESET1_SDRAM (1 << 1) 37d2a3b501SZev Weiss #define AST2600_WDT_RESET1_AHB (1 << 2) 38d2a3b501SZev Weiss #define AST2600_WDT_RESET1_SLI (1 << 3) 39d2a3b501SZev Weiss #define AST2600_WDT_RESET1_SOC_MISC0 (1 << 4) 40d2a3b501SZev Weiss #define AST2600_WDT_RESET1_COPROC (1 << 5) 41d2a3b501SZev Weiss #define AST2600_WDT_RESET1_USB_A (1 << 6) 42d2a3b501SZev Weiss #define AST2600_WDT_RESET1_USB_B (1 << 7) 43d2a3b501SZev Weiss #define AST2600_WDT_RESET1_UHCI (1 << 8) 44d2a3b501SZev Weiss #define AST2600_WDT_RESET1_GRAPHICS (1 << 9) 45d2a3b501SZev Weiss #define AST2600_WDT_RESET1_CRT (1 << 10) 46d2a3b501SZev Weiss #define AST2600_WDT_RESET1_VIDEO (1 << 11) 47d2a3b501SZev Weiss #define AST2600_WDT_RESET1_HAC (1 << 12) 48d2a3b501SZev Weiss #define AST2600_WDT_RESET1_DP (1 << 13) 49d2a3b501SZev Weiss #define AST2600_WDT_RESET1_DP_MCU (1 << 14) 50d2a3b501SZev Weiss #define AST2600_WDT_RESET1_GP_MCU (1 << 15) 51d2a3b501SZev Weiss #define AST2600_WDT_RESET1_MAC0 (1 << 16) 52d2a3b501SZev Weiss #define AST2600_WDT_RESET1_MAC1 (1 << 17) 53d2a3b501SZev Weiss #define AST2600_WDT_RESET1_SDIO0 (1 << 18) 54d2a3b501SZev Weiss #define AST2600_WDT_RESET1_JTAG0 (1 << 19) 55d2a3b501SZev Weiss #define AST2600_WDT_RESET1_MCTP0 (1 << 20) 56d2a3b501SZev Weiss #define AST2600_WDT_RESET1_MCTP1 (1 << 21) 57d2a3b501SZev Weiss #define AST2600_WDT_RESET1_XDMA0 (1 << 22) 58d2a3b501SZev Weiss #define AST2600_WDT_RESET1_XDMA1 (1 << 23) 59d2a3b501SZev Weiss #define AST2600_WDT_RESET1_GPIO0 (1 << 24) 60d2a3b501SZev Weiss #define AST2600_WDT_RESET1_RVAS (1 << 25) 61d2a3b501SZev Weiss 62d2a3b501SZev Weiss #define AST2600_WDT_RESET1_DEFAULT 0x030f1ff1 63d2a3b501SZev Weiss 64d2a3b501SZev Weiss #define AST2600_WDT_RESET2_CPU (1 << 0) 65d2a3b501SZev Weiss #define AST2600_WDT_RESET2_SPI (1 << 1) 66d2a3b501SZev Weiss #define AST2600_WDT_RESET2_AHB2 (1 << 2) 67d2a3b501SZev Weiss #define AST2600_WDT_RESET2_SLI2 (1 << 3) 68d2a3b501SZev Weiss #define AST2600_WDT_RESET2_SOC_MISC1 (1 << 4) 69d2a3b501SZev Weiss #define AST2600_WDT_RESET2_MAC2 (1 << 5) 70d2a3b501SZev Weiss #define AST2600_WDT_RESET2_MAC3 (1 << 6) 71d2a3b501SZev Weiss #define AST2600_WDT_RESET2_SDIO1 (1 << 7) 72d2a3b501SZev Weiss #define AST2600_WDT_RESET2_JTAG1 (1 << 8) 73d2a3b501SZev Weiss #define AST2600_WDT_RESET2_GPIO1 (1 << 9) 74d2a3b501SZev Weiss #define AST2600_WDT_RESET2_MDIO (1 << 10) 75d2a3b501SZev Weiss #define AST2600_WDT_RESET2_LPC (1 << 11) 76d2a3b501SZev Weiss #define AST2600_WDT_RESET2_PECI (1 << 12) 77d2a3b501SZev Weiss #define AST2600_WDT_RESET2_PWM (1 << 13) 78d2a3b501SZev Weiss #define AST2600_WDT_RESET2_ADC (1 << 14) 79d2a3b501SZev Weiss #define AST2600_WDT_RESET2_FSI (1 << 15) 80d2a3b501SZev Weiss #define AST2600_WDT_RESET2_I2C (1 << 16) 81d2a3b501SZev Weiss #define AST2600_WDT_RESET2_I3C_GLOBAL (1 << 17) 82d2a3b501SZev Weiss #define AST2600_WDT_RESET2_I3C0 (1 << 18) 83d2a3b501SZev Weiss #define AST2600_WDT_RESET2_I3C1 (1 << 19) 84d2a3b501SZev Weiss #define AST2600_WDT_RESET2_I3C2 (1 << 20) 85d2a3b501SZev Weiss #define AST2600_WDT_RESET2_I3C3 (1 << 21) 86d2a3b501SZev Weiss #define AST2600_WDT_RESET2_I3C4 (1 << 22) 87d2a3b501SZev Weiss #define AST2600_WDT_RESET2_I3C5 (1 << 23) 88d2a3b501SZev Weiss #define AST2600_WDT_RESET2_ESPI (1 << 26) 89d2a3b501SZev Weiss 90d2a3b501SZev Weiss #define AST2600_WDT_RESET2_DEFAULT 0x03fffff1 91d2a3b501SZev Weiss 92d2a3b501SZev Weiss #endif 93