1*498e2f7aSBalsam CHIHI /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*498e2f7aSBalsam CHIHI /*
3*498e2f7aSBalsam CHIHI  * Copyright (c) 2023 MediaTek Inc.
4*498e2f7aSBalsam CHIHI  * Author: Balsam CHIHI <bchihi@baylibre.com>
5*498e2f7aSBalsam CHIHI  */
6*498e2f7aSBalsam CHIHI 
7*498e2f7aSBalsam CHIHI #ifndef __MEDIATEK_LVTS_DT_H
8*498e2f7aSBalsam CHIHI #define __MEDIATEK_LVTS_DT_H
9*498e2f7aSBalsam CHIHI 
10*498e2f7aSBalsam CHIHI #define MT8195_MCU_BIG_CPU0     0
11*498e2f7aSBalsam CHIHI #define MT8195_MCU_BIG_CPU1     1
12*498e2f7aSBalsam CHIHI #define MT8195_MCU_BIG_CPU2     2
13*498e2f7aSBalsam CHIHI #define MT8195_MCU_BIG_CPU3     3
14*498e2f7aSBalsam CHIHI #define MT8195_MCU_LITTLE_CPU0  4
15*498e2f7aSBalsam CHIHI #define MT8195_MCU_LITTLE_CPU1  5
16*498e2f7aSBalsam CHIHI #define MT8195_MCU_LITTLE_CPU2  6
17*498e2f7aSBalsam CHIHI #define MT8195_MCU_LITTLE_CPU3  7
18*498e2f7aSBalsam CHIHI 
19*498e2f7aSBalsam CHIHI #endif /* __MEDIATEK_LVTS_DT_H */
20