1498e2f7aSBalsam CHIHI /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2498e2f7aSBalsam CHIHI /* 3498e2f7aSBalsam CHIHI * Copyright (c) 2023 MediaTek Inc. 4498e2f7aSBalsam CHIHI * Author: Balsam CHIHI <bchihi@baylibre.com> 5498e2f7aSBalsam CHIHI */ 6498e2f7aSBalsam CHIHI 7498e2f7aSBalsam CHIHI #ifndef __MEDIATEK_LVTS_DT_H 8498e2f7aSBalsam CHIHI #define __MEDIATEK_LVTS_DT_H 9498e2f7aSBalsam CHIHI 10498e2f7aSBalsam CHIHI #define MT8195_MCU_BIG_CPU0 0 11498e2f7aSBalsam CHIHI #define MT8195_MCU_BIG_CPU1 1 12498e2f7aSBalsam CHIHI #define MT8195_MCU_BIG_CPU2 2 13498e2f7aSBalsam CHIHI #define MT8195_MCU_BIG_CPU3 3 14498e2f7aSBalsam CHIHI #define MT8195_MCU_LITTLE_CPU0 4 15498e2f7aSBalsam CHIHI #define MT8195_MCU_LITTLE_CPU1 5 16498e2f7aSBalsam CHIHI #define MT8195_MCU_LITTLE_CPU2 6 17498e2f7aSBalsam CHIHI #define MT8195_MCU_LITTLE_CPU3 7 18498e2f7aSBalsam CHIHI 19*05aaa7fdSBalsam CHIHI #define MT8195_AP_VPU0 8 20*05aaa7fdSBalsam CHIHI #define MT8195_AP_VPU1 9 21*05aaa7fdSBalsam CHIHI #define MT8195_AP_GPU0 10 22*05aaa7fdSBalsam CHIHI #define MT8195_AP_GPU1 11 23*05aaa7fdSBalsam CHIHI #define MT8195_AP_VDEC 12 24*05aaa7fdSBalsam CHIHI #define MT8195_AP_IMG 13 25*05aaa7fdSBalsam CHIHI #define MT8195_AP_INFRA 14 26*05aaa7fdSBalsam CHIHI #define MT8195_AP_CAM0 15 27*05aaa7fdSBalsam CHIHI #define MT8195_AP_CAM1 16 28*05aaa7fdSBalsam CHIHI 29498e2f7aSBalsam CHIHI #endif /* __MEDIATEK_LVTS_DT_H */ 30