163313c1cSAndreas Färber /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ 263313c1cSAndreas Färber /* 363313c1cSAndreas Färber * Realtek RTD1195 reset controllers 463313c1cSAndreas Färber * 563313c1cSAndreas Färber * Copyright (c) 2017 Andreas Färber 663313c1cSAndreas Färber */ 763313c1cSAndreas Färber #ifndef DT_BINDINGS_RESET_RTD1195_H 863313c1cSAndreas Färber #define DT_BINDINGS_RESET_RTD1195_H 963313c1cSAndreas Färber 1063313c1cSAndreas Färber /* soft reset 1 */ 1163313c1cSAndreas Färber #define RTD1195_RSTN_MISC 0 1263313c1cSAndreas Färber #define RTD1195_RSTN_RNG 1 1363313c1cSAndreas Färber #define RTD1195_RSTN_USB3_POW 2 1463313c1cSAndreas Färber #define RTD1195_RSTN_GSPI 3 1563313c1cSAndreas Färber #define RTD1195_RSTN_USB3_P0_MDIO 4 1663313c1cSAndreas Färber #define RTD1195_RSTN_VE_H265 5 1763313c1cSAndreas Färber #define RTD1195_RSTN_USB 6 1863313c1cSAndreas Färber #define RTD1195_RSTN_USB_PHY0 8 1963313c1cSAndreas Färber #define RTD1195_RSTN_USB_PHY1 9 2063313c1cSAndreas Färber #define RTD1195_RSTN_HDMIRX 11 2163313c1cSAndreas Färber #define RTD1195_RSTN_HDMI 12 2263313c1cSAndreas Färber #define RTD1195_RSTN_ETN 14 2363313c1cSAndreas Färber #define RTD1195_RSTN_AIO 15 2463313c1cSAndreas Färber #define RTD1195_RSTN_GPU 16 2563313c1cSAndreas Färber #define RTD1195_RSTN_VE_H264 17 2663313c1cSAndreas Färber #define RTD1195_RSTN_VE_JPEG 18 2763313c1cSAndreas Färber #define RTD1195_RSTN_TVE 19 2863313c1cSAndreas Färber #define RTD1195_RSTN_VO 20 2963313c1cSAndreas Färber #define RTD1195_RSTN_LVDS 21 3063313c1cSAndreas Färber #define RTD1195_RSTN_SE 22 3163313c1cSAndreas Färber #define RTD1195_RSTN_DCU 23 3263313c1cSAndreas Färber #define RTD1195_RSTN_DC_PHY 24 3363313c1cSAndreas Färber #define RTD1195_RSTN_CP 25 3463313c1cSAndreas Färber #define RTD1195_RSTN_MD 26 3563313c1cSAndreas Färber #define RTD1195_RSTN_TP 27 3663313c1cSAndreas Färber #define RTD1195_RSTN_AE 28 3763313c1cSAndreas Färber #define RTD1195_RSTN_NF 29 3863313c1cSAndreas Färber #define RTD1195_RSTN_MIPI 30 3963313c1cSAndreas Färber 4063313c1cSAndreas Färber /* soft reset 2 */ 4163313c1cSAndreas Färber #define RTD1195_RSTN_ACPU 0 4263313c1cSAndreas Färber #define RTD1195_RSTN_VCPU 1 4363313c1cSAndreas Färber #define RTD1195_RSTN_PCR 9 4463313c1cSAndreas Färber #define RTD1195_RSTN_CR 10 4563313c1cSAndreas Färber #define RTD1195_RSTN_EMMC 11 4663313c1cSAndreas Färber #define RTD1195_RSTN_SDIO 12 4763313c1cSAndreas Färber #define RTD1195_RSTN_I2C_5 18 4863313c1cSAndreas Färber #define RTD1195_RSTN_RTC 20 4963313c1cSAndreas Färber #define RTD1195_RSTN_I2C_4 23 5063313c1cSAndreas Färber #define RTD1195_RSTN_I2C_3 24 5163313c1cSAndreas Färber #define RTD1195_RSTN_I2C_2 25 5263313c1cSAndreas Färber #define RTD1195_RSTN_I2C_1 26 5363313c1cSAndreas Färber #define RTD1195_RSTN_UR1 28 5463313c1cSAndreas Färber 5563313c1cSAndreas Färber /* soft reset 3 */ 5663313c1cSAndreas Färber #define RTD1195_RSTN_SB2 0 5763313c1cSAndreas Färber 5863313c1cSAndreas Färber /* iso soft reset */ 5963313c1cSAndreas Färber #define RTD1195_ISO_RSTN_VFD 0 6063313c1cSAndreas Färber #define RTD1195_ISO_RSTN_IR 1 6163313c1cSAndreas Färber #define RTD1195_ISO_RSTN_CEC0 2 6263313c1cSAndreas Färber #define RTD1195_ISO_RSTN_CEC1 3 6363313c1cSAndreas Färber #define RTD1195_ISO_RSTN_DP 4 6463313c1cSAndreas Färber #define RTD1195_ISO_RSTN_CBUSTX 5 6563313c1cSAndreas Färber #define RTD1195_ISO_RSTN_CBUSRX 6 6663313c1cSAndreas Färber #define RTD1195_ISO_RSTN_EFUSE 7 6763313c1cSAndreas Färber #define RTD1195_ISO_RSTN_UR0 8 6863313c1cSAndreas Färber #define RTD1195_ISO_RSTN_GMAC 9 6963313c1cSAndreas Färber #define RTD1195_ISO_RSTN_GPHY 10 7063313c1cSAndreas Färber #define RTD1195_ISO_RSTN_I2C_0 11 7163313c1cSAndreas Färber #define RTD1195_ISO_RSTN_I2C_6 12 7263313c1cSAndreas Färber #define RTD1195_ISO_RSTN_CBUS 13 7363313c1cSAndreas Färber 7463313c1cSAndreas Färber #endif 75