10eeff27bSStephen Boyd /*
20eeff27bSStephen Boyd  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
30eeff27bSStephen Boyd  *
40eeff27bSStephen Boyd  * This software is licensed under the terms of the GNU General Public
50eeff27bSStephen Boyd  * License version 2, as published by the Free Software Foundation, and
60eeff27bSStephen Boyd  * may be copied, distributed, and modified under those terms.
70eeff27bSStephen Boyd  *
80eeff27bSStephen Boyd  * This program is distributed in the hope that it will be useful,
90eeff27bSStephen Boyd  * but WITHOUT ANY WARRANTY; without even the implied warranty of
100eeff27bSStephen Boyd  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
110eeff27bSStephen Boyd  * GNU General Public License for more details.
120eeff27bSStephen Boyd  */
130eeff27bSStephen Boyd 
140eeff27bSStephen Boyd #ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H
150eeff27bSStephen Boyd #define _DT_BINDINGS_RESET_MSM_GCC_8660_H
160eeff27bSStephen Boyd 
170eeff27bSStephen Boyd #define AFAB_CORE_RESET					0
180eeff27bSStephen Boyd #define SCSS_SYS_RESET					1
190eeff27bSStephen Boyd #define SCSS_SYS_POR_RESET				2
200eeff27bSStephen Boyd #define AFAB_SMPSS_S_RESET				3
210eeff27bSStephen Boyd #define AFAB_SMPSS_M1_RESET				4
220eeff27bSStephen Boyd #define AFAB_SMPSS_M0_RESET				5
230eeff27bSStephen Boyd #define AFAB_EBI1_S_RESET				6
240eeff27bSStephen Boyd #define SFAB_CORE_RESET					7
250eeff27bSStephen Boyd #define SFAB_ADM0_M0_RESET				8
260eeff27bSStephen Boyd #define SFAB_ADM0_M1_RESET				9
270eeff27bSStephen Boyd #define SFAB_ADM0_M2_RESET				10
280eeff27bSStephen Boyd #define ADM0_C2_RESET					11
290eeff27bSStephen Boyd #define ADM0_C1_RESET					12
300eeff27bSStephen Boyd #define ADM0_C0_RESET					13
310eeff27bSStephen Boyd #define ADM0_PBUS_RESET					14
320eeff27bSStephen Boyd #define ADM0_RESET					15
330eeff27bSStephen Boyd #define SFAB_ADM1_M0_RESET				16
340eeff27bSStephen Boyd #define SFAB_ADM1_M1_RESET				17
350eeff27bSStephen Boyd #define SFAB_ADM1_M2_RESET				18
360eeff27bSStephen Boyd #define MMFAB_ADM1_M3_RESET				19
370eeff27bSStephen Boyd #define ADM1_C3_RESET					20
380eeff27bSStephen Boyd #define ADM1_C2_RESET					21
390eeff27bSStephen Boyd #define ADM1_C1_RESET					22
400eeff27bSStephen Boyd #define ADM1_C0_RESET					23
410eeff27bSStephen Boyd #define ADM1_PBUS_RESET					24
420eeff27bSStephen Boyd #define ADM1_RESET					25
430eeff27bSStephen Boyd #define IMEM0_RESET					26
440eeff27bSStephen Boyd #define SFAB_LPASS_Q6_RESET				27
450eeff27bSStephen Boyd #define SFAB_AFAB_M_RESET				28
460eeff27bSStephen Boyd #define AFAB_SFAB_M0_RESET				29
470eeff27bSStephen Boyd #define AFAB_SFAB_M1_RESET				30
480eeff27bSStephen Boyd #define DFAB_CORE_RESET					31
490eeff27bSStephen Boyd #define SFAB_DFAB_M_RESET				32
500eeff27bSStephen Boyd #define DFAB_SFAB_M_RESET				33
510eeff27bSStephen Boyd #define DFAB_SWAY0_RESET				34
520eeff27bSStephen Boyd #define DFAB_SWAY1_RESET				35
530eeff27bSStephen Boyd #define DFAB_ARB0_RESET					36
540eeff27bSStephen Boyd #define DFAB_ARB1_RESET					37
550eeff27bSStephen Boyd #define PPSS_PROC_RESET					38
560eeff27bSStephen Boyd #define PPSS_RESET					39
570eeff27bSStephen Boyd #define PMEM_RESET					40
580eeff27bSStephen Boyd #define DMA_BAM_RESET					41
590eeff27bSStephen Boyd #define SIC_RESET					42
600eeff27bSStephen Boyd #define SPS_TIC_RESET					43
610eeff27bSStephen Boyd #define CFBP0_RESET					44
620eeff27bSStephen Boyd #define CFBP1_RESET					45
630eeff27bSStephen Boyd #define CFBP2_RESET					46
640eeff27bSStephen Boyd #define EBI2_RESET					47
650eeff27bSStephen Boyd #define SFAB_CFPB_M_RESET				48
660eeff27bSStephen Boyd #define CFPB_MASTER_RESET				49
670eeff27bSStephen Boyd #define SFAB_CFPB_S_RESET				50
680eeff27bSStephen Boyd #define CFPB_SPLITTER_RESET				51
690eeff27bSStephen Boyd #define TSIF_RESET					52
700eeff27bSStephen Boyd #define CE1_RESET					53
710eeff27bSStephen Boyd #define CE2_RESET					54
720eeff27bSStephen Boyd #define SFAB_SFPB_M_RESET				55
730eeff27bSStephen Boyd #define SFAB_SFPB_S_RESET				56
740eeff27bSStephen Boyd #define RPM_PROC_RESET					57
750eeff27bSStephen Boyd #define RPM_BUS_RESET					58
760eeff27bSStephen Boyd #define RPM_MSG_RAM_RESET				59
770eeff27bSStephen Boyd #define PMIC_ARB0_RESET					60
780eeff27bSStephen Boyd #define PMIC_ARB1_RESET					61
790eeff27bSStephen Boyd #define PMIC_SSBI2_RESET				62
800eeff27bSStephen Boyd #define SDC1_RESET					63
810eeff27bSStephen Boyd #define SDC2_RESET					64
820eeff27bSStephen Boyd #define SDC3_RESET					65
830eeff27bSStephen Boyd #define SDC4_RESET					66
840eeff27bSStephen Boyd #define SDC5_RESET					67
850eeff27bSStephen Boyd #define USB_HS1_RESET					68
860eeff27bSStephen Boyd #define USB_HS2_XCVR_RESET				69
870eeff27bSStephen Boyd #define USB_HS2_RESET					70
880eeff27bSStephen Boyd #define USB_FS1_XCVR_RESET				71
890eeff27bSStephen Boyd #define USB_FS1_RESET					72
900eeff27bSStephen Boyd #define USB_FS2_XCVR_RESET				73
910eeff27bSStephen Boyd #define USB_FS2_RESET					74
920eeff27bSStephen Boyd #define GSBI1_RESET					75
930eeff27bSStephen Boyd #define GSBI2_RESET					76
940eeff27bSStephen Boyd #define GSBI3_RESET					77
950eeff27bSStephen Boyd #define GSBI4_RESET					78
960eeff27bSStephen Boyd #define GSBI5_RESET					79
970eeff27bSStephen Boyd #define GSBI6_RESET					80
980eeff27bSStephen Boyd #define GSBI7_RESET					81
990eeff27bSStephen Boyd #define GSBI8_RESET					82
1000eeff27bSStephen Boyd #define GSBI9_RESET					83
1010eeff27bSStephen Boyd #define GSBI10_RESET					84
1020eeff27bSStephen Boyd #define GSBI11_RESET					85
1030eeff27bSStephen Boyd #define GSBI12_RESET					86
1040eeff27bSStephen Boyd #define SPDM_RESET					87
1050eeff27bSStephen Boyd #define SEC_CTRL_RESET					88
1060eeff27bSStephen Boyd #define TLMM_H_RESET					89
1070eeff27bSStephen Boyd #define TLMM_RESET					90
1080eeff27bSStephen Boyd #define MARRM_PWRON_RESET				91
1090eeff27bSStephen Boyd #define MARM_RESET					92
1100eeff27bSStephen Boyd #define MAHB1_RESET					93
1110eeff27bSStephen Boyd #define SFAB_MSS_S_RESET				94
1120eeff27bSStephen Boyd #define MAHB2_RESET					95
1130eeff27bSStephen Boyd #define MODEM_SW_AHB_RESET				96
1140eeff27bSStephen Boyd #define MODEM_RESET					97
1150eeff27bSStephen Boyd #define SFAB_MSS_MDM1_RESET				98
1160eeff27bSStephen Boyd #define SFAB_MSS_MDM0_RESET				99
1170eeff27bSStephen Boyd #define MSS_SLP_RESET					100
1180eeff27bSStephen Boyd #define MSS_MARM_SAW_RESET				101
1190eeff27bSStephen Boyd #define MSS_WDOG_RESET					102
1200eeff27bSStephen Boyd #define TSSC_RESET					103
1210eeff27bSStephen Boyd #define PDM_RESET					104
1220eeff27bSStephen Boyd #define SCSS_CORE0_RESET				105
1230eeff27bSStephen Boyd #define SCSS_CORE0_POR_RESET				106
1240eeff27bSStephen Boyd #define SCSS_CORE1_RESET				107
1250eeff27bSStephen Boyd #define SCSS_CORE1_POR_RESET				108
1260eeff27bSStephen Boyd #define MPM_RESET					109
1270eeff27bSStephen Boyd #define EBI1_1X_DIV_RESET				110
1280eeff27bSStephen Boyd #define EBI1_RESET					111
1290eeff27bSStephen Boyd #define SFAB_SMPSS_S_RESET				112
1300eeff27bSStephen Boyd #define USB_PHY0_RESET					113
1310eeff27bSStephen Boyd #define USB_PHY1_RESET					114
1320eeff27bSStephen Boyd #define PRNG_RESET					115
1330eeff27bSStephen Boyd 
1340eeff27bSStephen Boyd #endif
135