1d15b1ff1SSricharan R /* SPDX-License-Identifier: GPL-2.0 */
2d15b1ff1SSricharan R /*
3d15b1ff1SSricharan R  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4d15b1ff1SSricharan R  */
5d15b1ff1SSricharan R 
6d15b1ff1SSricharan R #ifndef _DT_BINDINGS_RESET_IPQ_GCC_6018_H
7d15b1ff1SSricharan R #define _DT_BINDINGS_RESET_IPQ_GCC_6018_H
8d15b1ff1SSricharan R 
9d15b1ff1SSricharan R #define GCC_BLSP1_BCR				0
10d15b1ff1SSricharan R #define GCC_BLSP1_QUP1_BCR			1
11d15b1ff1SSricharan R #define GCC_BLSP1_UART1_BCR			2
12d15b1ff1SSricharan R #define GCC_BLSP1_QUP2_BCR			3
13d15b1ff1SSricharan R #define GCC_BLSP1_UART2_BCR			4
14d15b1ff1SSricharan R #define GCC_BLSP1_QUP3_BCR			5
15d15b1ff1SSricharan R #define GCC_BLSP1_UART3_BCR			6
16d15b1ff1SSricharan R #define GCC_BLSP1_QUP4_BCR			7
17d15b1ff1SSricharan R #define GCC_BLSP1_UART4_BCR			8
18d15b1ff1SSricharan R #define GCC_BLSP1_QUP5_BCR			9
19d15b1ff1SSricharan R #define GCC_BLSP1_UART5_BCR			10
20d15b1ff1SSricharan R #define GCC_BLSP1_QUP6_BCR			11
21d15b1ff1SSricharan R #define GCC_BLSP1_UART6_BCR			12
22d15b1ff1SSricharan R #define GCC_IMEM_BCR				13
23d15b1ff1SSricharan R #define GCC_SMMU_BCR				14
24d15b1ff1SSricharan R #define GCC_APSS_TCU_BCR			15
25d15b1ff1SSricharan R #define GCC_SMMU_XPU_BCR			16
26d15b1ff1SSricharan R #define GCC_PCNOC_TBU_BCR			17
27d15b1ff1SSricharan R #define GCC_SMMU_CFG_BCR			18
28d15b1ff1SSricharan R #define GCC_PRNG_BCR				19
29d15b1ff1SSricharan R #define GCC_BOOT_ROM_BCR			20
30d15b1ff1SSricharan R #define GCC_CRYPTO_BCR				21
31d15b1ff1SSricharan R #define GCC_WCSS_BCR				22
32d15b1ff1SSricharan R #define GCC_WCSS_Q6_BCR				23
33d15b1ff1SSricharan R #define GCC_NSS_BCR				24
34d15b1ff1SSricharan R #define GCC_SEC_CTRL_BCR			25
35d15b1ff1SSricharan R #define GCC_DDRSS_BCR				26
36d15b1ff1SSricharan R #define GCC_SYSTEM_NOC_BCR			27
37d15b1ff1SSricharan R #define GCC_PCNOC_BCR				28
38d15b1ff1SSricharan R #define GCC_TCSR_BCR				29
39d15b1ff1SSricharan R #define GCC_QDSS_BCR				30
40d15b1ff1SSricharan R #define GCC_DCD_BCR				31
41d15b1ff1SSricharan R #define GCC_MSG_RAM_BCR				32
42d15b1ff1SSricharan R #define GCC_MPM_BCR				33
43d15b1ff1SSricharan R #define GCC_SPDM_BCR				34
44d15b1ff1SSricharan R #define GCC_RBCPR_BCR				35
45d15b1ff1SSricharan R #define GCC_RBCPR_MX_BCR			36
46d15b1ff1SSricharan R #define GCC_TLMM_BCR				37
47d15b1ff1SSricharan R #define GCC_RBCPR_WCSS_BCR			38
48d15b1ff1SSricharan R #define GCC_USB0_PHY_BCR			39
49d15b1ff1SSricharan R #define GCC_USB3PHY_0_PHY_BCR			40
50d15b1ff1SSricharan R #define GCC_USB0_BCR				41
51d15b1ff1SSricharan R #define GCC_USB1_BCR				42
52d15b1ff1SSricharan R #define GCC_QUSB2_0_PHY_BCR			43
53d15b1ff1SSricharan R #define GCC_QUSB2_1_PHY_BCR			44
54d15b1ff1SSricharan R #define GCC_SDCC1_BCR				45
55d15b1ff1SSricharan R #define GCC_SNOC_BUS_TIMEOUT0_BCR		46
56d15b1ff1SSricharan R #define GCC_SNOC_BUS_TIMEOUT1_BCR		47
57d15b1ff1SSricharan R #define GCC_SNOC_BUS_TIMEOUT2_BCR		48
58d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT0_BCR		49
59d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT1_BCR		50
60d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT2_BCR		51
61d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT3_BCR		52
62d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT4_BCR		53
63d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT5_BCR		54
64d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT6_BCR		55
65d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT7_BCR		56
66d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT8_BCR		57
67d15b1ff1SSricharan R #define GCC_PCNOC_BUS_TIMEOUT9_BCR		58
68d15b1ff1SSricharan R #define GCC_UNIPHY0_BCR				59
69d15b1ff1SSricharan R #define GCC_UNIPHY1_BCR				60
70d15b1ff1SSricharan R #define GCC_CMN_12GPLL_BCR			61
71d15b1ff1SSricharan R #define GCC_QPIC_BCR				62
72d15b1ff1SSricharan R #define GCC_MDIO_BCR				63
73d15b1ff1SSricharan R #define GCC_WCSS_CORE_TBU_BCR			64
74d15b1ff1SSricharan R #define GCC_WCSS_Q6_TBU_BCR			65
75d15b1ff1SSricharan R #define GCC_USB0_TBU_BCR			66
76d15b1ff1SSricharan R #define GCC_PCIE0_TBU_BCR			67
77d15b1ff1SSricharan R #define GCC_PCIE0_BCR				68
78d15b1ff1SSricharan R #define GCC_PCIE0_PHY_BCR			69
79d15b1ff1SSricharan R #define GCC_PCIE0PHY_PHY_BCR			70
80d15b1ff1SSricharan R #define GCC_PCIE0_LINK_DOWN_BCR			71
81d15b1ff1SSricharan R #define GCC_DCC_BCR				72
82d15b1ff1SSricharan R #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR	73
83d15b1ff1SSricharan R #define GCC_SMMU_CATS_BCR			74
84d15b1ff1SSricharan R #define GCC_UBI0_AXI_ARES			75
85d15b1ff1SSricharan R #define GCC_UBI0_AHB_ARES			76
86d15b1ff1SSricharan R #define GCC_UBI0_NC_AXI_ARES			77
87d15b1ff1SSricharan R #define GCC_UBI0_DBG_ARES			78
88d15b1ff1SSricharan R #define GCC_UBI0_CORE_CLAMP_ENABLE		79
89d15b1ff1SSricharan R #define GCC_UBI0_CLKRST_CLAMP_ENABLE		80
90d15b1ff1SSricharan R #define GCC_UBI0_UTCM_ARES			81
91d15b1ff1SSricharan R #define GCC_NSS_CFG_ARES			82
92d15b1ff1SSricharan R #define GCC_NSS_NOC_ARES			83
93d15b1ff1SSricharan R #define GCC_NSS_CRYPTO_ARES			84
94d15b1ff1SSricharan R #define GCC_NSS_CSR_ARES			85
95d15b1ff1SSricharan R #define GCC_NSS_CE_APB_ARES			86
96d15b1ff1SSricharan R #define GCC_NSS_CE_AXI_ARES			87
97d15b1ff1SSricharan R #define GCC_NSSNOC_CE_APB_ARES			88
98d15b1ff1SSricharan R #define GCC_NSSNOC_CE_AXI_ARES			89
99d15b1ff1SSricharan R #define GCC_NSSNOC_UBI0_AHB_ARES		90
100d15b1ff1SSricharan R #define GCC_NSSNOC_SNOC_ARES			91
101d15b1ff1SSricharan R #define GCC_NSSNOC_CRYPTO_ARES			92
102d15b1ff1SSricharan R #define GCC_NSSNOC_ATB_ARES			93
103d15b1ff1SSricharan R #define GCC_NSSNOC_QOSGEN_REF_ARES		94
104d15b1ff1SSricharan R #define GCC_NSSNOC_TIMEOUT_REF_ARES		95
105d15b1ff1SSricharan R #define GCC_PCIE0_PIPE_ARES			96
106d15b1ff1SSricharan R #define GCC_PCIE0_SLEEP_ARES			97
107d15b1ff1SSricharan R #define GCC_PCIE0_CORE_STICKY_ARES		98
108d15b1ff1SSricharan R #define GCC_PCIE0_AXI_MASTER_ARES		99
109d15b1ff1SSricharan R #define GCC_PCIE0_AXI_SLAVE_ARES		100
110d15b1ff1SSricharan R #define GCC_PCIE0_AHB_ARES			101
111d15b1ff1SSricharan R #define GCC_PCIE0_AXI_MASTER_STICKY_ARES	102
112d15b1ff1SSricharan R #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		103
113d15b1ff1SSricharan R #define GCC_PPE_FULL_RESET			104
114d15b1ff1SSricharan R #define GCC_UNIPHY0_SOFT_RESET			105
115d15b1ff1SSricharan R #define GCC_UNIPHY0_XPCS_RESET			106
116d15b1ff1SSricharan R #define GCC_UNIPHY1_SOFT_RESET			107
117d15b1ff1SSricharan R #define GCC_UNIPHY1_XPCS_RESET			108
118d15b1ff1SSricharan R #define GCC_EDMA_HW_RESET			109
119d15b1ff1SSricharan R #define GCC_ADSS_BCR				110
120d15b1ff1SSricharan R #define GCC_NSS_NOC_TBU_BCR			111
121d15b1ff1SSricharan R #define GCC_NSSPORT1_RESET			112
122d15b1ff1SSricharan R #define GCC_NSSPORT2_RESET			113
123d15b1ff1SSricharan R #define GCC_NSSPORT3_RESET			114
124d15b1ff1SSricharan R #define GCC_NSSPORT4_RESET			115
125d15b1ff1SSricharan R #define GCC_NSSPORT5_RESET			116
126d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT1_ARES			117
127d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT2_ARES			118
128d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT3_ARES			119
129d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT4_ARES			120
130d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT5_ARES			121
131d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT_4_5_RESET		122
132d15b1ff1SSricharan R #define GCC_UNIPHY0_PORT_4_RESET		123
133d15b1ff1SSricharan R #define GCC_LPASS_BCR				124
134d15b1ff1SSricharan R #define GCC_UBI32_TBU_BCR			125
135d15b1ff1SSricharan R #define GCC_LPASS_TBU_BCR			126
136d15b1ff1SSricharan R #define GCC_WCSSAON_RESET			127
137d15b1ff1SSricharan R #define GCC_LPASS_Q6_AXIM_ARES			128
138d15b1ff1SSricharan R #define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES		129
139d15b1ff1SSricharan R #define GCC_LPASS_Q6SS_TRIG_ARES		130
140d15b1ff1SSricharan R #define GCC_LPASS_Q6_ATBM_AT_ARES		131
141d15b1ff1SSricharan R #define GCC_LPASS_Q6_PCLKDBG_ARES		132
142d15b1ff1SSricharan R #define GCC_LPASS_CORE_AXIM_ARES		133
143d15b1ff1SSricharan R #define GCC_LPASS_SNOC_CFG_ARES			134
144d15b1ff1SSricharan R #define GCC_WCSS_DBG_ARES			135
145d15b1ff1SSricharan R #define GCC_WCSS_ECAHB_ARES			136
146d15b1ff1SSricharan R #define GCC_WCSS_ACMT_ARES			137
147d15b1ff1SSricharan R #define GCC_WCSS_DBG_BDG_ARES			138
148d15b1ff1SSricharan R #define GCC_WCSS_AHB_S_ARES			139
149d15b1ff1SSricharan R #define GCC_WCSS_AXI_M_ARES			140
150d15b1ff1SSricharan R #define GCC_Q6SS_DBG_ARES			141
151d15b1ff1SSricharan R #define GCC_Q6_AHB_S_ARES			142
152d15b1ff1SSricharan R #define GCC_Q6_AHB_ARES				143
153d15b1ff1SSricharan R #define GCC_Q6_AXIM2_ARES			144
154d15b1ff1SSricharan R #define GCC_Q6_AXIM_ARES			145
155d15b1ff1SSricharan R #define GCC_UBI0_CORE_ARES			146
156d15b1ff1SSricharan R 
157d15b1ff1SSricharan R #endif
158