1*476650a6SJacky Huang /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*476650a6SJacky Huang /* 3*476650a6SJacky Huang * Copyright (C) 2023 Nuvoton Technologies. 4*476650a6SJacky Huang * Author: Chi-Fen Li <cfli0@nuvoton.com> 5*476650a6SJacky Huang * 6*476650a6SJacky Huang * Device Tree binding constants for MA35D1 reset controller. 7*476650a6SJacky Huang */ 8*476650a6SJacky Huang 9*476650a6SJacky Huang #ifndef __DT_BINDINGS_RESET_MA35D1_H 10*476650a6SJacky Huang #define __DT_BINDINGS_RESET_MA35D1_H 11*476650a6SJacky Huang 12*476650a6SJacky Huang #define MA35D1_RESET_CHIP 0 13*476650a6SJacky Huang #define MA35D1_RESET_CA35CR0 1 14*476650a6SJacky Huang #define MA35D1_RESET_CA35CR1 2 15*476650a6SJacky Huang #define MA35D1_RESET_CM4 3 16*476650a6SJacky Huang #define MA35D1_RESET_PDMA0 4 17*476650a6SJacky Huang #define MA35D1_RESET_PDMA1 5 18*476650a6SJacky Huang #define MA35D1_RESET_PDMA2 6 19*476650a6SJacky Huang #define MA35D1_RESET_PDMA3 7 20*476650a6SJacky Huang #define MA35D1_RESET_DISP 8 21*476650a6SJacky Huang #define MA35D1_RESET_VCAP0 9 22*476650a6SJacky Huang #define MA35D1_RESET_VCAP1 10 23*476650a6SJacky Huang #define MA35D1_RESET_GFX 11 24*476650a6SJacky Huang #define MA35D1_RESET_VDEC 12 25*476650a6SJacky Huang #define MA35D1_RESET_WHC0 13 26*476650a6SJacky Huang #define MA35D1_RESET_WHC1 14 27*476650a6SJacky Huang #define MA35D1_RESET_GMAC0 15 28*476650a6SJacky Huang #define MA35D1_RESET_GMAC1 16 29*476650a6SJacky Huang #define MA35D1_RESET_HWSEM 17 30*476650a6SJacky Huang #define MA35D1_RESET_EBI 18 31*476650a6SJacky Huang #define MA35D1_RESET_HSUSBH0 19 32*476650a6SJacky Huang #define MA35D1_RESET_HSUSBH1 20 33*476650a6SJacky Huang #define MA35D1_RESET_HSUSBD 21 34*476650a6SJacky Huang #define MA35D1_RESET_USBHL 22 35*476650a6SJacky Huang #define MA35D1_RESET_SDH0 23 36*476650a6SJacky Huang #define MA35D1_RESET_SDH1 24 37*476650a6SJacky Huang #define MA35D1_RESET_NAND 25 38*476650a6SJacky Huang #define MA35D1_RESET_GPIO 26 39*476650a6SJacky Huang #define MA35D1_RESET_MCTLP 27 40*476650a6SJacky Huang #define MA35D1_RESET_MCTLC 28 41*476650a6SJacky Huang #define MA35D1_RESET_DDRPUB 29 42*476650a6SJacky Huang #define MA35D1_RESET_TMR0 30 43*476650a6SJacky Huang #define MA35D1_RESET_TMR1 31 44*476650a6SJacky Huang #define MA35D1_RESET_TMR2 32 45*476650a6SJacky Huang #define MA35D1_RESET_TMR3 33 46*476650a6SJacky Huang #define MA35D1_RESET_I2C0 34 47*476650a6SJacky Huang #define MA35D1_RESET_I2C1 35 48*476650a6SJacky Huang #define MA35D1_RESET_I2C2 36 49*476650a6SJacky Huang #define MA35D1_RESET_I2C3 37 50*476650a6SJacky Huang #define MA35D1_RESET_QSPI0 38 51*476650a6SJacky Huang #define MA35D1_RESET_SPI0 39 52*476650a6SJacky Huang #define MA35D1_RESET_SPI1 40 53*476650a6SJacky Huang #define MA35D1_RESET_SPI2 41 54*476650a6SJacky Huang #define MA35D1_RESET_UART0 42 55*476650a6SJacky Huang #define MA35D1_RESET_UART1 43 56*476650a6SJacky Huang #define MA35D1_RESET_UART2 44 57*476650a6SJacky Huang #define MA35D1_RESET_UART3 45 58*476650a6SJacky Huang #define MA35D1_RESET_UART4 46 59*476650a6SJacky Huang #define MA35D1_RESET_UART5 47 60*476650a6SJacky Huang #define MA35D1_RESET_UART6 48 61*476650a6SJacky Huang #define MA35D1_RESET_UART7 49 62*476650a6SJacky Huang #define MA35D1_RESET_CANFD0 50 63*476650a6SJacky Huang #define MA35D1_RESET_CANFD1 51 64*476650a6SJacky Huang #define MA35D1_RESET_EADC0 52 65*476650a6SJacky Huang #define MA35D1_RESET_I2S0 53 66*476650a6SJacky Huang #define MA35D1_RESET_SC0 54 67*476650a6SJacky Huang #define MA35D1_RESET_SC1 55 68*476650a6SJacky Huang #define MA35D1_RESET_QSPI1 56 69*476650a6SJacky Huang #define MA35D1_RESET_SPI3 57 70*476650a6SJacky Huang #define MA35D1_RESET_EPWM0 58 71*476650a6SJacky Huang #define MA35D1_RESET_EPWM1 59 72*476650a6SJacky Huang #define MA35D1_RESET_QEI0 60 73*476650a6SJacky Huang #define MA35D1_RESET_QEI1 61 74*476650a6SJacky Huang #define MA35D1_RESET_ECAP0 62 75*476650a6SJacky Huang #define MA35D1_RESET_ECAP1 63 76*476650a6SJacky Huang #define MA35D1_RESET_CANFD2 64 77*476650a6SJacky Huang #define MA35D1_RESET_ADC0 65 78*476650a6SJacky Huang #define MA35D1_RESET_TMR4 66 79*476650a6SJacky Huang #define MA35D1_RESET_TMR5 67 80*476650a6SJacky Huang #define MA35D1_RESET_TMR6 68 81*476650a6SJacky Huang #define MA35D1_RESET_TMR7 69 82*476650a6SJacky Huang #define MA35D1_RESET_TMR8 70 83*476650a6SJacky Huang #define MA35D1_RESET_TMR9 71 84*476650a6SJacky Huang #define MA35D1_RESET_TMR10 72 85*476650a6SJacky Huang #define MA35D1_RESET_TMR11 73 86*476650a6SJacky Huang #define MA35D1_RESET_UART8 74 87*476650a6SJacky Huang #define MA35D1_RESET_UART9 75 88*476650a6SJacky Huang #define MA35D1_RESET_UART10 76 89*476650a6SJacky Huang #define MA35D1_RESET_UART11 77 90*476650a6SJacky Huang #define MA35D1_RESET_UART12 78 91*476650a6SJacky Huang #define MA35D1_RESET_UART13 79 92*476650a6SJacky Huang #define MA35D1_RESET_UART14 80 93*476650a6SJacky Huang #define MA35D1_RESET_UART15 81 94*476650a6SJacky Huang #define MA35D1_RESET_UART16 82 95*476650a6SJacky Huang #define MA35D1_RESET_I2S1 83 96*476650a6SJacky Huang #define MA35D1_RESET_I2C4 84 97*476650a6SJacky Huang #define MA35D1_RESET_I2C5 85 98*476650a6SJacky Huang #define MA35D1_RESET_EPWM2 86 99*476650a6SJacky Huang #define MA35D1_RESET_ECAP2 87 100*476650a6SJacky Huang #define MA35D1_RESET_QEI2 88 101*476650a6SJacky Huang #define MA35D1_RESET_CANFD3 89 102*476650a6SJacky Huang #define MA35D1_RESET_KPI 90 103*476650a6SJacky Huang #define MA35D1_RESET_GIC 91 104*476650a6SJacky Huang #define MA35D1_RESET_SSMCC 92 105*476650a6SJacky Huang #define MA35D1_RESET_SSPCC 93 106*476650a6SJacky Huang #define MA35D1_RESET_COUNT 94 107*476650a6SJacky Huang 108*476650a6SJacky Huang #endif 109