1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Christine Zhu <christine.zhu@mediatek.com> 5 */ 6 7 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 8 #define _DT_BINDINGS_RESET_CONTROLLER_MT8195 9 10 /* TOPRGU resets */ 11 #define MT8195_TOPRGU_CONN_MCU_SW_RST 0 12 #define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 13 #define MT8195_TOPRGU_APU_SW_RST 2 14 #define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 15 #define MT8195_TOPRGU_MMSYS_SW_RST 7 16 #define MT8195_TOPRGU_MFG_SW_RST 8 17 #define MT8195_TOPRGU_VENC_SW_RST 9 18 #define MT8195_TOPRGU_VDEC_SW_RST 10 19 #define MT8195_TOPRGU_IMG_SW_RST 11 20 #define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 21 #define MT8195_TOPRGU_AUDIO_SW_RST 14 22 #define MT8195_TOPRGU_CAMSYS_SW_RST 15 23 #define MT8195_TOPRGU_EDPTX_SW_RST 16 24 #define MT8195_TOPRGU_ADSPSYS_SW_RST 21 25 #define MT8195_TOPRGU_DPTX_SW_RST 22 26 #define MT8195_TOPRGU_SPMI_MST_SW_RST 23 27 28 #define MT8195_TOPRGU_SW_RST_NUM 16 29 30 /* INFRA resets */ 31 #define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0 32 #define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1 33 #define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2 34 #define MT8195_INFRA_RST2_PCIE_P0_SWRST 3 35 #define MT8195_INFRA_RST2_PCIE_P1_SWRST 4 36 37 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ 38