1f07c776fSEnric Balletbo i Serra /* SPDX-License-Identifier: GPL-2.0 */ 2f07c776fSEnric Balletbo i Serra /* 3f07c776fSEnric Balletbo i Serra * Copyright (c) 2020 MediaTek Inc. 4f07c776fSEnric Balletbo i Serra * Author: Yong Liang <yong.liang@mediatek.com> 5f07c776fSEnric Balletbo i Serra */ 6f07c776fSEnric Balletbo i Serra 7f07c776fSEnric Balletbo i Serra #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 8f07c776fSEnric Balletbo i Serra #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 9f07c776fSEnric Balletbo i Serra 10*fb91526bSRex-BC Chen /* TOPRGU resets */ 11f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_MM_SW_RST 1 12f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_MFG_SW_RST 2 13f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_VENC_SW_RST 3 14f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_VDEC_SW_RST 4 15f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_IMG_SW_RST 5 16f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_MD_SW_RST 7 17f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_CONN_SW_RST 9 18f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_CONN_MCU_SW_RST 12 19f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_IPU0_SW_RST 14 20f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_IPU1_SW_RST 15 21f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_AUDIO_SW_RST 17 22f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_CAMSYS_SW_RST 18 23f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_MJC_SW_RST 19 24f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_C2K_S2_SW_RST 20 25f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_C2K_SW_RST 21 26f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_PERI_SW_RST 22 27f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_PERI_AO_SW_RST 23 28f07c776fSEnric Balletbo i Serra 29f07c776fSEnric Balletbo i Serra #define MT8192_TOPRGU_SW_RST_NUM 23 30f07c776fSEnric Balletbo i Serra 3119c66219SAllen-KH Cheng /* MMSYS resets */ 3219c66219SAllen-KH Cheng #define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15 3319c66219SAllen-KH Cheng 34*fb91526bSRex-BC Chen /* INFRA resets */ 35*fb91526bSRex-BC Chen #define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0 36*fb91526bSRex-BC Chen #define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1 37*fb91526bSRex-BC Chen #define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2 38*fb91526bSRex-BC Chen #define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3 39*fb91526bSRex-BC Chen #define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4 40*fb91526bSRex-BC Chen 41f07c776fSEnric Balletbo i Serra #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ 42