1*fea58041SRunyang Chen /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
2*fea58041SRunyang Chen /*
3*fea58041SRunyang Chen  * Copyright (c) 2022 MediaTek Inc.
4*fea58041SRunyang Chen  * Author: Runyang Chen <runyang.chen@mediatek.com>
5*fea58041SRunyang Chen  */
6*fea58041SRunyang Chen 
7*fea58041SRunyang Chen #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188
8*fea58041SRunyang Chen #define _DT_BINDINGS_RESET_CONTROLLER_MT8188
9*fea58041SRunyang Chen 
10*fea58041SRunyang Chen #define MT8188_TOPRGU_CONN_MCU_SW_RST          0
11*fea58041SRunyang Chen #define MT8188_TOPRGU_INFRA_GRST_SW_RST        1
12*fea58041SRunyang Chen #define MT8188_TOPRGU_IPU0_SW_RST              2
13*fea58041SRunyang Chen #define MT8188_TOPRGU_IPU1_SW_RST              3
14*fea58041SRunyang Chen #define MT8188_TOPRGU_IPU2_SW_RST              4
15*fea58041SRunyang Chen #define MT8188_TOPRGU_AUD_ASRC_SW_RST          5
16*fea58041SRunyang Chen #define MT8188_TOPRGU_INFRA_SW_RST             6
17*fea58041SRunyang Chen #define MT8188_TOPRGU_MMSYS_SW_RST             7
18*fea58041SRunyang Chen #define MT8188_TOPRGU_MFG_SW_RST               8
19*fea58041SRunyang Chen #define MT8188_TOPRGU_VENC_SW_RST              9
20*fea58041SRunyang Chen #define MT8188_TOPRGU_VDEC_SW_RST              10
21*fea58041SRunyang Chen #define MT8188_TOPRGU_CAM_VCORE_SW_RST         11
22*fea58041SRunyang Chen #define MT8188_TOPRGU_SCP_SW_RST               12
23*fea58041SRunyang Chen #define MT8188_TOPRGU_APMIXEDSYS_SW_RST        13
24*fea58041SRunyang Chen #define MT8188_TOPRGU_AUDIO_SW_RST             14
25*fea58041SRunyang Chen #define MT8188_TOPRGU_CAMSYS_SW_RST            15
26*fea58041SRunyang Chen #define MT8188_TOPRGU_MJC_SW_RST               16
27*fea58041SRunyang Chen #define MT8188_TOPRGU_PERI_SW_RST              17
28*fea58041SRunyang Chen #define MT8188_TOPRGU_PERI_AO_SW_RST           18
29*fea58041SRunyang Chen #define MT8188_TOPRGU_PCIE_SW_RST              19
30*fea58041SRunyang Chen #define MT8188_TOPRGU_ADSPSYS_SW_RST           21
31*fea58041SRunyang Chen #define MT8188_TOPRGU_DPTX_SW_RST              22
32*fea58041SRunyang Chen #define MT8188_TOPRGU_SPMI_MST_SW_RST          23
33*fea58041SRunyang Chen 
34*fea58041SRunyang Chen #define MT8188_TOPRGU_SW_RST_NUM               24
35*fea58041SRunyang Chen 
36*fea58041SRunyang Chen #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
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