1fea58041SRunyang Chen /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ 2fea58041SRunyang Chen /* 3fea58041SRunyang Chen * Copyright (c) 2022 MediaTek Inc. 4fea58041SRunyang Chen * Author: Runyang Chen <runyang.chen@mediatek.com> 5fea58041SRunyang Chen */ 6fea58041SRunyang Chen 7fea58041SRunyang Chen #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188 8fea58041SRunyang Chen #define _DT_BINDINGS_RESET_CONTROLLER_MT8188 9fea58041SRunyang Chen 10fea58041SRunyang Chen #define MT8188_TOPRGU_CONN_MCU_SW_RST 0 11fea58041SRunyang Chen #define MT8188_TOPRGU_INFRA_GRST_SW_RST 1 12fea58041SRunyang Chen #define MT8188_TOPRGU_IPU0_SW_RST 2 13fea58041SRunyang Chen #define MT8188_TOPRGU_IPU1_SW_RST 3 14fea58041SRunyang Chen #define MT8188_TOPRGU_IPU2_SW_RST 4 15fea58041SRunyang Chen #define MT8188_TOPRGU_AUD_ASRC_SW_RST 5 16fea58041SRunyang Chen #define MT8188_TOPRGU_INFRA_SW_RST 6 17fea58041SRunyang Chen #define MT8188_TOPRGU_MMSYS_SW_RST 7 18fea58041SRunyang Chen #define MT8188_TOPRGU_MFG_SW_RST 8 19fea58041SRunyang Chen #define MT8188_TOPRGU_VENC_SW_RST 9 20fea58041SRunyang Chen #define MT8188_TOPRGU_VDEC_SW_RST 10 21fea58041SRunyang Chen #define MT8188_TOPRGU_CAM_VCORE_SW_RST 11 22fea58041SRunyang Chen #define MT8188_TOPRGU_SCP_SW_RST 12 23fea58041SRunyang Chen #define MT8188_TOPRGU_APMIXEDSYS_SW_RST 13 24fea58041SRunyang Chen #define MT8188_TOPRGU_AUDIO_SW_RST 14 25fea58041SRunyang Chen #define MT8188_TOPRGU_CAMSYS_SW_RST 15 26fea58041SRunyang Chen #define MT8188_TOPRGU_MJC_SW_RST 16 27fea58041SRunyang Chen #define MT8188_TOPRGU_PERI_SW_RST 17 28fea58041SRunyang Chen #define MT8188_TOPRGU_PERI_AO_SW_RST 18 29fea58041SRunyang Chen #define MT8188_TOPRGU_PCIE_SW_RST 19 30fea58041SRunyang Chen #define MT8188_TOPRGU_ADSPSYS_SW_RST 21 31fea58041SRunyang Chen #define MT8188_TOPRGU_DPTX_SW_RST 22 32fea58041SRunyang Chen #define MT8188_TOPRGU_SPMI_MST_SW_RST 23 33fea58041SRunyang Chen 34fea58041SRunyang Chen #define MT8188_TOPRGU_SW_RST_NUM 24 35fea58041SRunyang Chen 36*2cf4ec53SRunyang Chen /* INFRA resets */ 37*2cf4ec53SRunyang Chen #define MT8188_INFRA_RST1_THERMAL_MCU_RST 0 38*2cf4ec53SRunyang Chen #define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1 39*2cf4ec53SRunyang Chen #define MT8188_INFRA_RST3_PTP_CTRL_RST 2 40*2cf4ec53SRunyang Chen 41fea58041SRunyang Chen #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ 42