1967313e2SPhilipp Zabel /* 2967313e2SPhilipp Zabel * Copyright (c) 2014 MediaTek Inc. 3967313e2SPhilipp Zabel * Author: Flora Fu, MediaTek 4967313e2SPhilipp Zabel * 5967313e2SPhilipp Zabel * This program is free software; you can redistribute it and/or modify 6967313e2SPhilipp Zabel * it under the terms of the GNU General Public License version 2 as 7967313e2SPhilipp Zabel * published by the Free Software Foundation. 8967313e2SPhilipp Zabel * 9967313e2SPhilipp Zabel * This program is distributed in the hope that it will be useful, 10967313e2SPhilipp Zabel * but WITHOUT ANY WARRANTY; without even the implied warranty of 11967313e2SPhilipp Zabel * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12967313e2SPhilipp Zabel * GNU General Public License for more details. 13967313e2SPhilipp Zabel */ 14967313e2SPhilipp Zabel 15967313e2SPhilipp Zabel #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 16967313e2SPhilipp Zabel #define _DT_BINDINGS_RESET_CONTROLLER_MT8173 17967313e2SPhilipp Zabel 18967313e2SPhilipp Zabel /* INFRACFG resets */ 19967313e2SPhilipp Zabel #define MT8173_INFRA_EMI_REG_RST 0 20967313e2SPhilipp Zabel #define MT8173_INFRA_DRAMC0_A0_RST 1 21967313e2SPhilipp Zabel #define MT8173_INFRA_APCIRQ_EINT_RST 3 22967313e2SPhilipp Zabel #define MT8173_INFRA_APXGPT_RST 4 23967313e2SPhilipp Zabel #define MT8173_INFRA_SCPSYS_RST 5 24967313e2SPhilipp Zabel #define MT8173_INFRA_KP_RST 6 25967313e2SPhilipp Zabel #define MT8173_INFRA_PMIC_WRAP_RST 7 26967313e2SPhilipp Zabel #define MT8173_INFRA_MPIP_RST 8 27967313e2SPhilipp Zabel #define MT8173_INFRA_CEC_RST 9 28967313e2SPhilipp Zabel #define MT8173_INFRA_EMI_RST 32 29967313e2SPhilipp Zabel #define MT8173_INFRA_DRAMC0_RST 34 30967313e2SPhilipp Zabel #define MT8173_INFRA_APMIXEDSYS_RST 35 31967313e2SPhilipp Zabel #define MT8173_INFRA_MIPI_DSI_RST 36 32967313e2SPhilipp Zabel #define MT8173_INFRA_TRNG_RST 37 33967313e2SPhilipp Zabel #define MT8173_INFRA_SYSIRQ_RST 38 34967313e2SPhilipp Zabel #define MT8173_INFRA_MIPI_CSI_RST 39 35967313e2SPhilipp Zabel #define MT8173_INFRA_GCE_FAXI_RST 40 36967313e2SPhilipp Zabel #define MT8173_INFRA_MMIOMMURST 47 37967313e2SPhilipp Zabel 38967313e2SPhilipp Zabel 39967313e2SPhilipp Zabel /* PERICFG resets */ 40967313e2SPhilipp Zabel #define MT8173_PERI_UART0_SW_RST 0 41967313e2SPhilipp Zabel #define MT8173_PERI_UART1_SW_RST 1 42967313e2SPhilipp Zabel #define MT8173_PERI_UART2_SW_RST 2 43967313e2SPhilipp Zabel #define MT8173_PERI_UART3_SW_RST 3 44967313e2SPhilipp Zabel #define MT8173_PERI_IRRX_SW_RST 4 45967313e2SPhilipp Zabel #define MT8173_PERI_PWM_SW_RST 8 46967313e2SPhilipp Zabel #define MT8173_PERI_AUXADC_SW_RST 10 47967313e2SPhilipp Zabel #define MT8173_PERI_DMA_SW_RST 11 48967313e2SPhilipp Zabel #define MT8173_PERI_I2C6_SW_RST 13 49967313e2SPhilipp Zabel #define MT8173_PERI_NFI_SW_RST 14 50967313e2SPhilipp Zabel #define MT8173_PERI_THERM_SW_RST 16 51967313e2SPhilipp Zabel #define MT8173_PERI_MSDC2_SW_RST 17 52967313e2SPhilipp Zabel #define MT8173_PERI_MSDC3_SW_RST 18 53967313e2SPhilipp Zabel #define MT8173_PERI_MSDC0_SW_RST 19 54967313e2SPhilipp Zabel #define MT8173_PERI_MSDC1_SW_RST 20 55967313e2SPhilipp Zabel #define MT8173_PERI_I2C0_SW_RST 22 56967313e2SPhilipp Zabel #define MT8173_PERI_I2C1_SW_RST 23 57967313e2SPhilipp Zabel #define MT8173_PERI_I2C2_SW_RST 24 58967313e2SPhilipp Zabel #define MT8173_PERI_I2C3_SW_RST 25 59967313e2SPhilipp Zabel #define MT8173_PERI_I2C4_SW_RST 26 60967313e2SPhilipp Zabel #define MT8173_PERI_HDMI_SW_RST 29 61967313e2SPhilipp Zabel #define MT8173_PERI_SPI0_SW_RST 33 62967313e2SPhilipp Zabel 63967313e2SPhilipp Zabel #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ 64