11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2967313e2SPhilipp Zabel /* 3967313e2SPhilipp Zabel * Copyright (c) 2014 MediaTek Inc. 4967313e2SPhilipp Zabel * Author: Flora Fu, MediaTek 5967313e2SPhilipp Zabel */ 6967313e2SPhilipp Zabel 7967313e2SPhilipp Zabel #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 8967313e2SPhilipp Zabel #define _DT_BINDINGS_RESET_CONTROLLER_MT8173 9967313e2SPhilipp Zabel 10967313e2SPhilipp Zabel /* INFRACFG resets */ 11967313e2SPhilipp Zabel #define MT8173_INFRA_EMI_REG_RST 0 12967313e2SPhilipp Zabel #define MT8173_INFRA_DRAMC0_A0_RST 1 13967313e2SPhilipp Zabel #define MT8173_INFRA_APCIRQ_EINT_RST 3 14967313e2SPhilipp Zabel #define MT8173_INFRA_APXGPT_RST 4 15967313e2SPhilipp Zabel #define MT8173_INFRA_SCPSYS_RST 5 16967313e2SPhilipp Zabel #define MT8173_INFRA_KP_RST 6 17967313e2SPhilipp Zabel #define MT8173_INFRA_PMIC_WRAP_RST 7 18967313e2SPhilipp Zabel #define MT8173_INFRA_MPIP_RST 8 19967313e2SPhilipp Zabel #define MT8173_INFRA_CEC_RST 9 20967313e2SPhilipp Zabel #define MT8173_INFRA_EMI_RST 32 21967313e2SPhilipp Zabel #define MT8173_INFRA_DRAMC0_RST 34 22967313e2SPhilipp Zabel #define MT8173_INFRA_APMIXEDSYS_RST 35 23967313e2SPhilipp Zabel #define MT8173_INFRA_MIPI_DSI_RST 36 24967313e2SPhilipp Zabel #define MT8173_INFRA_TRNG_RST 37 25967313e2SPhilipp Zabel #define MT8173_INFRA_SYSIRQ_RST 38 26967313e2SPhilipp Zabel #define MT8173_INFRA_MIPI_CSI_RST 39 27967313e2SPhilipp Zabel #define MT8173_INFRA_GCE_FAXI_RST 40 28967313e2SPhilipp Zabel #define MT8173_INFRA_MMIOMMURST 47 29967313e2SPhilipp Zabel 30967313e2SPhilipp Zabel 31967313e2SPhilipp Zabel /* PERICFG resets */ 32967313e2SPhilipp Zabel #define MT8173_PERI_UART0_SW_RST 0 33967313e2SPhilipp Zabel #define MT8173_PERI_UART1_SW_RST 1 34967313e2SPhilipp Zabel #define MT8173_PERI_UART2_SW_RST 2 35967313e2SPhilipp Zabel #define MT8173_PERI_UART3_SW_RST 3 36967313e2SPhilipp Zabel #define MT8173_PERI_IRRX_SW_RST 4 37967313e2SPhilipp Zabel #define MT8173_PERI_PWM_SW_RST 8 38967313e2SPhilipp Zabel #define MT8173_PERI_AUXADC_SW_RST 10 39967313e2SPhilipp Zabel #define MT8173_PERI_DMA_SW_RST 11 40967313e2SPhilipp Zabel #define MT8173_PERI_I2C6_SW_RST 13 41967313e2SPhilipp Zabel #define MT8173_PERI_NFI_SW_RST 14 42967313e2SPhilipp Zabel #define MT8173_PERI_THERM_SW_RST 16 43967313e2SPhilipp Zabel #define MT8173_PERI_MSDC2_SW_RST 17 44967313e2SPhilipp Zabel #define MT8173_PERI_MSDC3_SW_RST 18 45967313e2SPhilipp Zabel #define MT8173_PERI_MSDC0_SW_RST 19 46967313e2SPhilipp Zabel #define MT8173_PERI_MSDC1_SW_RST 20 47967313e2SPhilipp Zabel #define MT8173_PERI_I2C0_SW_RST 22 48967313e2SPhilipp Zabel #define MT8173_PERI_I2C1_SW_RST 23 49967313e2SPhilipp Zabel #define MT8173_PERI_I2C2_SW_RST 24 50967313e2SPhilipp Zabel #define MT8173_PERI_I2C3_SW_RST 25 51967313e2SPhilipp Zabel #define MT8173_PERI_I2C4_SW_RST 26 52967313e2SPhilipp Zabel #define MT8173_PERI_HDMI_SW_RST 29 53967313e2SPhilipp Zabel #define MT8173_PERI_SPI0_SW_RST 33 54967313e2SPhilipp Zabel 55967313e2SPhilipp Zabel #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ 56