1967313e2SPhilipp Zabel /* 2967313e2SPhilipp Zabel * Copyright (c) 2014 MediaTek Inc. 3967313e2SPhilipp Zabel * Author: Flora Fu, MediaTek 4967313e2SPhilipp Zabel * 5967313e2SPhilipp Zabel * This program is free software; you can redistribute it and/or modify 6967313e2SPhilipp Zabel * it under the terms of the GNU General Public License version 2 as 7967313e2SPhilipp Zabel * published by the Free Software Foundation. 8967313e2SPhilipp Zabel * 9967313e2SPhilipp Zabel * This program is distributed in the hope that it will be useful, 10967313e2SPhilipp Zabel * but WITHOUT ANY WARRANTY; without even the implied warranty of 11967313e2SPhilipp Zabel * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12967313e2SPhilipp Zabel * GNU General Public License for more details. 13967313e2SPhilipp Zabel */ 14967313e2SPhilipp Zabel 15967313e2SPhilipp Zabel #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 16967313e2SPhilipp Zabel #define _DT_BINDINGS_RESET_CONTROLLER_MT8135 17967313e2SPhilipp Zabel 18967313e2SPhilipp Zabel /* INFRACFG resets */ 19967313e2SPhilipp Zabel #define MT8135_INFRA_EMI_REG_RST 0 20967313e2SPhilipp Zabel #define MT8135_INFRA_DRAMC0_A0_RST 1 21967313e2SPhilipp Zabel #define MT8135_INFRA_CCIF0_RST 2 22967313e2SPhilipp Zabel #define MT8135_INFRA_APCIRQ_EINT_RST 3 23967313e2SPhilipp Zabel #define MT8135_INFRA_APXGPT_RST 4 24967313e2SPhilipp Zabel #define MT8135_INFRA_SCPSYS_RST 5 25967313e2SPhilipp Zabel #define MT8135_INFRA_CCIF1_RST 6 26967313e2SPhilipp Zabel #define MT8135_INFRA_PMIC_WRAP_RST 7 27967313e2SPhilipp Zabel #define MT8135_INFRA_KP_RST 8 28967313e2SPhilipp Zabel #define MT8135_INFRA_EMI_RST 32 29967313e2SPhilipp Zabel #define MT8135_INFRA_DRAMC0_RST 34 30967313e2SPhilipp Zabel #define MT8135_INFRA_SMI_RST 35 31967313e2SPhilipp Zabel #define MT8135_INFRA_M4U_RST 36 32967313e2SPhilipp Zabel 33967313e2SPhilipp Zabel /* PERICFG resets */ 34967313e2SPhilipp Zabel #define MT8135_PERI_UART0_SW_RST 0 35967313e2SPhilipp Zabel #define MT8135_PERI_UART1_SW_RST 1 36967313e2SPhilipp Zabel #define MT8135_PERI_UART2_SW_RST 2 37967313e2SPhilipp Zabel #define MT8135_PERI_UART3_SW_RST 3 38967313e2SPhilipp Zabel #define MT8135_PERI_IRDA_SW_RST 4 39967313e2SPhilipp Zabel #define MT8135_PERI_PTP_SW_RST 5 40967313e2SPhilipp Zabel #define MT8135_PERI_AP_HIF_SW_RST 6 41967313e2SPhilipp Zabel #define MT8135_PERI_GPCU_SW_RST 7 42967313e2SPhilipp Zabel #define MT8135_PERI_MD_HIF_SW_RST 8 43967313e2SPhilipp Zabel #define MT8135_PERI_NLI_SW_RST 9 44967313e2SPhilipp Zabel #define MT8135_PERI_AUXADC_SW_RST 10 45967313e2SPhilipp Zabel #define MT8135_PERI_DMA_SW_RST 11 46967313e2SPhilipp Zabel #define MT8135_PERI_NFI_SW_RST 14 47967313e2SPhilipp Zabel #define MT8135_PERI_PWM_SW_RST 15 48967313e2SPhilipp Zabel #define MT8135_PERI_THERM_SW_RST 16 49967313e2SPhilipp Zabel #define MT8135_PERI_MSDC0_SW_RST 17 50967313e2SPhilipp Zabel #define MT8135_PERI_MSDC1_SW_RST 18 51967313e2SPhilipp Zabel #define MT8135_PERI_MSDC2_SW_RST 19 52967313e2SPhilipp Zabel #define MT8135_PERI_MSDC3_SW_RST 20 53967313e2SPhilipp Zabel #define MT8135_PERI_I2C0_SW_RST 22 54967313e2SPhilipp Zabel #define MT8135_PERI_I2C1_SW_RST 23 55967313e2SPhilipp Zabel #define MT8135_PERI_I2C2_SW_RST 24 56967313e2SPhilipp Zabel #define MT8135_PERI_I2C3_SW_RST 25 57967313e2SPhilipp Zabel #define MT8135_PERI_I2C4_SW_RST 26 58967313e2SPhilipp Zabel #define MT8135_PERI_I2C5_SW_RST 27 59967313e2SPhilipp Zabel #define MT8135_PERI_I2C6_SW_RST 28 60967313e2SPhilipp Zabel #define MT8135_PERI_USB_SW_RST 29 61967313e2SPhilipp Zabel #define MT8135_PERI_SPI1_SW_RST 33 62967313e2SPhilipp Zabel #define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 63967313e2SPhilipp Zabel 64967313e2SPhilipp Zabel #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ 65