11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2967313e2SPhilipp Zabel /* 3967313e2SPhilipp Zabel * Copyright (c) 2014 MediaTek Inc. 4967313e2SPhilipp Zabel * Author: Flora Fu, MediaTek 5967313e2SPhilipp Zabel */ 6967313e2SPhilipp Zabel 7967313e2SPhilipp Zabel #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 8967313e2SPhilipp Zabel #define _DT_BINDINGS_RESET_CONTROLLER_MT8135 9967313e2SPhilipp Zabel 10967313e2SPhilipp Zabel /* INFRACFG resets */ 11967313e2SPhilipp Zabel #define MT8135_INFRA_EMI_REG_RST 0 12967313e2SPhilipp Zabel #define MT8135_INFRA_DRAMC0_A0_RST 1 13967313e2SPhilipp Zabel #define MT8135_INFRA_CCIF0_RST 2 14967313e2SPhilipp Zabel #define MT8135_INFRA_APCIRQ_EINT_RST 3 15967313e2SPhilipp Zabel #define MT8135_INFRA_APXGPT_RST 4 16967313e2SPhilipp Zabel #define MT8135_INFRA_SCPSYS_RST 5 17967313e2SPhilipp Zabel #define MT8135_INFRA_CCIF1_RST 6 18967313e2SPhilipp Zabel #define MT8135_INFRA_PMIC_WRAP_RST 7 19967313e2SPhilipp Zabel #define MT8135_INFRA_KP_RST 8 20967313e2SPhilipp Zabel #define MT8135_INFRA_EMI_RST 32 21967313e2SPhilipp Zabel #define MT8135_INFRA_DRAMC0_RST 34 22967313e2SPhilipp Zabel #define MT8135_INFRA_SMI_RST 35 23967313e2SPhilipp Zabel #define MT8135_INFRA_M4U_RST 36 24967313e2SPhilipp Zabel 25967313e2SPhilipp Zabel /* PERICFG resets */ 26967313e2SPhilipp Zabel #define MT8135_PERI_UART0_SW_RST 0 27967313e2SPhilipp Zabel #define MT8135_PERI_UART1_SW_RST 1 28967313e2SPhilipp Zabel #define MT8135_PERI_UART2_SW_RST 2 29967313e2SPhilipp Zabel #define MT8135_PERI_UART3_SW_RST 3 30967313e2SPhilipp Zabel #define MT8135_PERI_IRDA_SW_RST 4 31967313e2SPhilipp Zabel #define MT8135_PERI_PTP_SW_RST 5 32967313e2SPhilipp Zabel #define MT8135_PERI_AP_HIF_SW_RST 6 33967313e2SPhilipp Zabel #define MT8135_PERI_GPCU_SW_RST 7 34967313e2SPhilipp Zabel #define MT8135_PERI_MD_HIF_SW_RST 8 35967313e2SPhilipp Zabel #define MT8135_PERI_NLI_SW_RST 9 36967313e2SPhilipp Zabel #define MT8135_PERI_AUXADC_SW_RST 10 37967313e2SPhilipp Zabel #define MT8135_PERI_DMA_SW_RST 11 38967313e2SPhilipp Zabel #define MT8135_PERI_NFI_SW_RST 14 39967313e2SPhilipp Zabel #define MT8135_PERI_PWM_SW_RST 15 40967313e2SPhilipp Zabel #define MT8135_PERI_THERM_SW_RST 16 41967313e2SPhilipp Zabel #define MT8135_PERI_MSDC0_SW_RST 17 42967313e2SPhilipp Zabel #define MT8135_PERI_MSDC1_SW_RST 18 43967313e2SPhilipp Zabel #define MT8135_PERI_MSDC2_SW_RST 19 44967313e2SPhilipp Zabel #define MT8135_PERI_MSDC3_SW_RST 20 45967313e2SPhilipp Zabel #define MT8135_PERI_I2C0_SW_RST 22 46967313e2SPhilipp Zabel #define MT8135_PERI_I2C1_SW_RST 23 47967313e2SPhilipp Zabel #define MT8135_PERI_I2C2_SW_RST 24 48967313e2SPhilipp Zabel #define MT8135_PERI_I2C3_SW_RST 25 49967313e2SPhilipp Zabel #define MT8135_PERI_I2C4_SW_RST 26 50967313e2SPhilipp Zabel #define MT8135_PERI_I2C5_SW_RST 27 51967313e2SPhilipp Zabel #define MT8135_PERI_I2C6_SW_RST 28 52967313e2SPhilipp Zabel #define MT8135_PERI_USB_SW_RST 29 53967313e2SPhilipp Zabel #define MT8135_PERI_SPI1_SW_RST 33 54967313e2SPhilipp Zabel #define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 55967313e2SPhilipp Zabel 56967313e2SPhilipp Zabel #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ 57