17f4fbf79SSean Wang /* 27f4fbf79SSean Wang * Copyright (c) 2017 MediaTek Inc. 37f4fbf79SSean Wang * Author: Sean Wang <sean.wang@mediatek.com> 47f4fbf79SSean Wang * 57f4fbf79SSean Wang * This program is free software; you can redistribute it and/or modify 67f4fbf79SSean Wang * it under the terms of the GNU General Public License version 2 as 77f4fbf79SSean Wang * published by the Free Software Foundation. 87f4fbf79SSean Wang * 97f4fbf79SSean Wang * This program is distributed in the hope that it will be useful, 107f4fbf79SSean Wang * but WITHOUT ANY WARRANTY; without even the implied warranty of 117f4fbf79SSean Wang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 127f4fbf79SSean Wang * GNU General Public License for more details. 137f4fbf79SSean Wang */ 147f4fbf79SSean Wang 157f4fbf79SSean Wang #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622 167f4fbf79SSean Wang #define _DT_BINDINGS_RESET_CONTROLLER_MT7622 177f4fbf79SSean Wang 187f4fbf79SSean Wang /* INFRACFG resets */ 197f4fbf79SSean Wang #define MT7622_INFRA_EMI_REG_RST 0 207f4fbf79SSean Wang #define MT7622_INFRA_DRAMC0_A0_RST 1 217f4fbf79SSean Wang #define MT7622_INFRA_APCIRQ_EINT_RST 3 227f4fbf79SSean Wang #define MT7622_INFRA_APXGPT_RST 4 237f4fbf79SSean Wang #define MT7622_INFRA_SCPSYS_RST 5 247f4fbf79SSean Wang #define MT7622_INFRA_PMIC_WRAP_RST 7 257f4fbf79SSean Wang #define MT7622_INFRA_IRRX_RST 9 267f4fbf79SSean Wang #define MT7622_INFRA_EMI_RST 16 277f4fbf79SSean Wang #define MT7622_INFRA_WED0_RST 17 287f4fbf79SSean Wang #define MT7622_INFRA_DRAMC_RST 18 297f4fbf79SSean Wang #define MT7622_INFRA_CCI_INTF_RST 19 307f4fbf79SSean Wang #define MT7622_INFRA_TRNG_RST 21 317f4fbf79SSean Wang #define MT7622_INFRA_SYSIRQ_RST 22 327f4fbf79SSean Wang #define MT7622_INFRA_WED1_RST 25 337f4fbf79SSean Wang 347f4fbf79SSean Wang /* PERICFG Subsystem resets */ 357f4fbf79SSean Wang #define MT7622_PERI_UART0_SW_RST 0 367f4fbf79SSean Wang #define MT7622_PERI_UART1_SW_RST 1 377f4fbf79SSean Wang #define MT7622_PERI_UART2_SW_RST 2 387f4fbf79SSean Wang #define MT7622_PERI_UART3_SW_RST 3 397f4fbf79SSean Wang #define MT7622_PERI_UART4_SW_RST 4 407f4fbf79SSean Wang #define MT7622_PERI_BTIF_SW_RST 6 417f4fbf79SSean Wang #define MT7622_PERI_PWM_SW_RST 8 427f4fbf79SSean Wang #define MT7622_PERI_AUXADC_SW_RST 10 437f4fbf79SSean Wang #define MT7622_PERI_DMA_SW_RST 11 447f4fbf79SSean Wang #define MT7622_PERI_IRTX_SW_RST 13 457f4fbf79SSean Wang #define MT7622_PERI_NFI_SW_RST 14 467f4fbf79SSean Wang #define MT7622_PERI_THERM_SW_RST 16 477f4fbf79SSean Wang #define MT7622_PERI_MSDC0_SW_RST 19 487f4fbf79SSean Wang #define MT7622_PERI_MSDC1_SW_RST 20 497f4fbf79SSean Wang #define MT7622_PERI_I2C0_SW_RST 22 507f4fbf79SSean Wang #define MT7622_PERI_I2C1_SW_RST 23 517f4fbf79SSean Wang #define MT7622_PERI_I2C2_SW_RST 24 527f4fbf79SSean Wang #define MT7622_PERI_SPI0_SW_RST 33 537f4fbf79SSean Wang #define MT7622_PERI_SPI1_SW_RST 34 547f4fbf79SSean Wang #define MT7622_PERI_FLASHIF_SW_RST 36 557f4fbf79SSean Wang 567f4fbf79SSean Wang /* TOPRGU resets */ 577f4fbf79SSean Wang #define MT7622_TOPRGU_INFRA_RST 0 587f4fbf79SSean Wang #define MT7622_TOPRGU_ETHDMA_RST 1 597f4fbf79SSean Wang #define MT7622_TOPRGU_DDRPHY_RST 6 607f4fbf79SSean Wang #define MT7622_TOPRGU_INFRA_AO_RST 8 617f4fbf79SSean Wang #define MT7622_TOPRGU_CONN_RST 9 627f4fbf79SSean Wang #define MT7622_TOPRGU_APMIXED_RST 10 637f4fbf79SSean Wang #define MT7622_TOPRGU_CONN_MCU_RST 12 647f4fbf79SSean Wang 657f4fbf79SSean Wang /* PCIe/SATA Subsystem resets */ 667f4fbf79SSean Wang #define MT7622_SATA_PHY_REG_RST 12 677f4fbf79SSean Wang #define MT7622_SATA_PHY_SW_RST 13 687f4fbf79SSean Wang #define MT7622_SATA_AXI_BUS_RST 15 697f4fbf79SSean Wang #define MT7622_PCIE1_CORE_RST 19 707f4fbf79SSean Wang #define MT7622_PCIE1_MMIO_RST 20 717f4fbf79SSean Wang #define MT7622_PCIE1_HRST 21 727f4fbf79SSean Wang #define MT7622_PCIE1_USER_RST 22 737f4fbf79SSean Wang #define MT7622_PCIE1_PIPE_RST 23 747f4fbf79SSean Wang #define MT7622_PCIE0_CORE_RST 27 757f4fbf79SSean Wang #define MT7622_PCIE0_MMIO_RST 28 767f4fbf79SSean Wang #define MT7622_PCIE0_HRST 29 777f4fbf79SSean Wang #define MT7622_PCIE0_USER_RST 30 787f4fbf79SSean Wang #define MT7622_PCIE0_PIPE_RST 31 797f4fbf79SSean Wang 807f4fbf79SSean Wang /* SSUSB Subsystem resets */ 817f4fbf79SSean Wang #define MT7622_SSUSB_PHY_PWR_RST 3 827f4fbf79SSean Wang #define MT7622_SSUSB_MAC_PWR_RST 4 837f4fbf79SSean Wang 847f4fbf79SSean Wang /* ETHSYS Subsystem resets */ 857f4fbf79SSean Wang #define MT7622_ETHSYS_SYS_RST 0 867f4fbf79SSean Wang #define MT7622_ETHSYS_MCM_RST 2 877f4fbf79SSean Wang #define MT7622_ETHSYS_HSDMA_RST 5 887f4fbf79SSean Wang #define MT7622_ETHSYS_FE_RST 6 897f4fbf79SSean Wang #define MT7622_ETHSYS_GMAC_RST 23 907f4fbf79SSean Wang #define MT7622_ETHSYS_EPHY_RST 24 917f4fbf79SSean Wang #define MT7622_ETHSYS_CRYPTO_RST 29 927f4fbf79SSean Wang #define MT7622_ETHSYS_PPE_RST 31 937f4fbf79SSean Wang 947f4fbf79SSean Wang #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */ 95